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24LC04BH-I/MS

更新时间： 2024-02-25 06:56:42

品牌	Logo	应用领域
美国微芯 - MICROCHIP		存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数	文件大小	规格书
28页	469K
描述
4K I2C™ Serial EEPROM with Half-Array Write-Protect

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24LC04BH-I/MS 技术参数

是否Rohs认证：	不符合	生命周期：	Active
Reach Compliance Code：	unknown	风险等级：	5.53
数据保留时间-最小值：	100	耐久性：	100000 Write/Erase Cycles
I2C控制字节：	1010DDMR	JESD-30 代码：	R-PDSO-G14
JESD-609代码：	e0	内存密度：	4096 bit
内存集成电路类型：	EEPROM	内存宽度：	8
端子数量：	14	字数：	512 words
字数代码：	512	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	512X8
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP14,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	SERIAL
电源：	3/5 V	认证状态：	Not Qualified
串行总线类型：	I2C	最大待机电流：	0.00003 A
子类别：	EEPROMs	最大压摆率：	0.003 mA
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	写保护：	HARDWARE
Base Number Matches：	1

24LC04BH-I/MS 数据手册

24AA04H/24LC04BH

3.4

Data Valid (D)

2.0

FUNCTIONAL DESCRIPTION

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The 24XX04H supports a bidirectional, 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as a transmitter, while a device

receiving data is defined as a receiver. The bus has to

be controlled by a master device which generates the

Serial Clock (SCL), controls the bus access and

generates the Start and Stop conditions, while the

24XX04H works as slave. Both master and slave can

operate as transmitter or receiver, but the master

device determines which mode is activated.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device and is

theoretically unlimited, although only the last sixteen

will be stored when doing a write operation. When an

overwrite does occur it will replace data in a first-in first-

out (FIFO) fashion.

3.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

3.5

Acknowledge

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

Note:

The 24XX04H does not generate any

Acknowledge bits if an internal program-

ming cycle is in progress.

3.1

Bus Not Busy (A)

The device that acknowledges, has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end of

data to the slave by not generating an Acknowledge bit

on the last byte that has been clocked out of the slave.

In this case, the slave (24XX04H) will leave the data

line high to enable the master to generate the Stop

condition.

Both data and clock lines remain high.

3.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

3.3

Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

SCL

SDA

Start

Condition

Stop

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

DS22119A-page 5

1 2 3 456 7 8...28

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