25AA640/25LC640/25C640
M
™
64K SPI Bus Serial EEPROM
PACKAGE TYPES
DEVICE SELECTION TABLE
Part
Number
VCC
Range
Max Clock
Frequency
Temp
Ranges
PDIP/SOIC
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
25AA640
25LC640
25C640
1.8-5.5V
2.5-5.5V
4.5-5.5V
1 MHz
2 MHz
3 MHz
C,I
C,I
C,I,E
WP
VSS
FEATURES
• Low power CMOS technology
- Write current: 3 mA typical
- Read current: 500 µA typical
- Standby current: 500 nA typical
• 8192 x 8 bit organization
• 32 byte page
• Write cycle time: 5ms max.
• Self-timed ERASE and WRITE cycles
• Block write protection
TSSOP
1
2
3
4
8
7
6
5
SCK
SI
VSS
WP
HOLD
VCC
CS
SO
- Protect none, 1/4, 1/2, or all of array
• Built-in write protection
- Power on/off data protection circuitry
- Write enable latch
BLOCK DIAGRAM
Status
Register
- Write protect pin
• Sequential read
HV Generator
• High reliability
- Endurance: 1M cycles (guaranteed)
- Data retention: > 200 years
- ESD protection: > 4000 V
• 8-pin PDIP, SOIC, and TSSOP packages
• Temperature ranges supported:
EEPROM
Array
Memory
Control
Logic
X
I/O Control
Logic
- Commercial: (C)
- Industrial: (I)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Dec
- Automotive: (E) (25C640)
Page Latches
DESCRIPTION
SI
The Microchip Technology Inc. 25AA640/25LC640/
25C640 (25xx640 ) is a 64K bit serial Electrically Eras-
*
Y Decoder
SO
able PROM. The memory is accessed via a simple
Serial Peripheral Interface (SPI) compatible serial bus.
The bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled through a chip select (CS) input.
CS
SCK
Sense Amp.
R/W Control
HOLD
WP
VCC
VSS
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
chip select, allowing the host to service higher priority
interrupts.
*25xx640 is used in this document as a generic part number for the 25AA640/25LC640/25C640 devices.
SPI is a trademark of Motorola.
1997 Microchip Technology Inc.
Preliminary
DS21223A-page 1