Datasheet > 249033-001

249033-001

更新时间： 2024-11-06 02:50:55

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
48页	789K
描述
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications

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249033-001 数据手册

LXT362

Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications

Datasheet

The LXT362 is a fully integrated, combination transceiver for T1 ISDN Primary Rate Interface

and general T1 long and short haul applications. It operates over 22 AWG twisted-pair cables

from 0 to 6 kft and offers Line Build Outs and pulse equalization settings for all T1 Line

Interface Unit (LIU) applications.

LXT362 provides both a serial port for microprocessor control (Host mode) as well as stand-

alone operation (Hardware mode). The device incorporates advanced crystal-less digital jitter

attenuation in either the transmit or receive data path starting at 3 Hz. B8ZS encoding/decoding

and unipolar or bipolar data I/O are selectable. Loss of signal monitoring and a variety of

diagnostic loopback modes can also be selected.

Applications

■ ISDN Primary Rate Interface (ISDN PRI)

■ CSU/NTU interface to T1 Service

■ Wireless Base Station interface

■ T1 LAN/WAN bridge/routers

■ T1 Mux; Channel Banks

■ Digital Loop Carrier - Subscriber Carrier

Systems

Product Features

■ Fully integrated transceiver for Long or

■ Four Line Build-Outs for T1 long-haul

Short-Haul T1 interfaces

applications from 0 dB to -22.5 dB

—Crystal-less digital jitter attenuation

—Select either transmit or receive path

■ Transmit/receive performance monitors

with Driver Fail Monitor Open and Loss of

Signal outputs

■ No crystal or high speed external clock

■ Selectable unipolar or bipolar data I/O and

required

B8ZS encoding/decoding

■ Meets or exceeds specifications in ANSI

T1.102, T1.403 and T1.408; and AT&T

Pub 62411

■ Line attenuation indication output in 2.9 dB

steps

■ QRSS generator/detector for testing or

■ Supports 100 Ω (T1 twisted-pair)

monitoring

applications

■ Local, remote, and analog loopback, plus

in-band network loopback code generation

and detection

■ Selectable receiver sensitivity – fully

restores the received signal after

transmission through a cable with

attenuation of either 0 to 26 dB, or 0 to

36 dB @ 772 kHz

■ Multiple register serial interface for

microprocessor control

■ Available in 28-pin PLCC, 44-pin PQFP,

■ Five Pulse Equalization Settings for T1

and 44-pin LQFP packages

short-haul applications

As of January 15, 2001, this document replaces the Level One document

known as LXT362 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications.

Order Number: 249033-001

January 2001

12 3 4 5 6 7...48

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