Datasheet > 240VA

240VA

更新时间： 2024-02-22 04:40:50

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
25页	324K
描述
In-System Programmable 3.3V Generic Digital CrosspointTM

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技术参数
数据手册

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240VA 技术参数

生命周期：	Active	Reach Compliance Code：	unknown
风险等级：	5.81	其他特性：	VSWR MAX AT 6 GHZ
特性阻抗：	50 Ω	连接器类型：	RF TNC CONNECTOR
联系完成配合：	NOT SPECIFIED	触点性别：	MALE
耦合类型：	THREADED	DIN 符合性：	NO
滤波功能：	NO	IEC 符合性：	NO
插入损耗：	0.12 dB	MIL 符合性：	NO
安装方式：	RIGHT ANGLE	安装类型：	CABLE
最大工作频率：	6 GHz	选件：	GENERAL PURPOSE
面板安装：	NO	端接类型：	CRIMP SOLDER
电压驻波比：	1.21	Base Number Matches：	1

240VA 数据手册

Specifications ispGDX240VA

Figure 3. Adjacent I/O Cells vs. Direct Input Path for

ispGDX240VA, I/O D33

Special Features

Slew Rate Control

ispGDX240VA I/O Cell

I/O Group A

All output buffers contain a programmable slew rate

control that provides software-selectable slew rate op-

tions.

D31 MUX Out

S1 S0

I/O Group B

.m0

Open Drain Control

4 x 4

Crossbar

Switch

D32 MUX Out

I/O Group C

.m1

.m2

D33

All output buffers provide a programmable Open-Drain

option which allows the user to drive system level reset,

interrupt and enable/disable lines directly without the

needforanoff-chipOpen-DrainorOpen-Collectorbuffer.

Wire-OR logic functions can be performed at the printed

circuit board level.

.m3

D34 MUX Out

I/O Group D

D35 MUX Out

It can be seen from Figure 3 that if the D11 adjacent I/O

cell is used, the I/O group “A” input is no longer available

as a direct MUX input.

Pull-up Resistor

All pins have a programmable active pull-up. A typical

resistor value for the pull-up ranges from 50kΩ to 80kΩ.

The ispGDXVA can implement MUXes up to 16 bits wide

in a single level of logic, but care must be taken when

combining adjacent I/O cell outputs with direct MUX

inputs.AnyparticularcombinationofadjacentI/Ocellsas

MUX inputs will dictate what I/O groups (A, B, C or D) can

be routed to the remaining inputs. By properly choosing

the adjacent I/O cells, all of the MUX inputs can be

utilized.

Output Latch (Bus Hold)

All pins have a programmable circuit that weakly holds

the previously driven state when all drivers connected to

the pin (including the pin's output driver as well as any

other devices connected to the pin by external bus) are

tristated.

Table 2. Adjacent I/O Cells (Mapping of

ispGDX240VA)

User-Programmable I/Os

The ispGDX240VA features user-programmable

I/Os supporting either 3.3V or 2.5V output voltage level

options. The ispGDX240VA uses a VCCIO pin to provide

the 2.5V reference voltage when used.

Data A/ Data B/ Data C/ Data D/

MUXOUT MUXOUT MUXOUT MUXOUT

B30

B31

B32

B33

D26

D27

D28

D29

D30

D31

D32

D33

B26

B27

B28

B29

B32

B33

B34

B35

D28

D29

D30

D31

D28

D29

D30

D31

B24

B25

B26

B27

B31

B32

B33

B34

D27

D28

D29

D30

D29

D30

D31

D32

B25

B26

B27

B28

B29

B30

B31

B32

D25

D26

D27

D28

D31

D32

D33

D34

B27

B28

B29

B30

B28

B29

B30

B31

D24

D25

D26

D27

D32

D33

D34

D35

B28

B29

B30

B31

PCI Compatible Drive Capability

Reflected

I/O Cells

The ispGDX240VA supports PCI compatible drive capa-

bility for all I/Os.

Normal

I/O Cells

1 2 3 456 7 8...25

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