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23S09E-1HPGGI8 PDF预览

23S09E-1HPGGI8

更新时间: 2024-11-21 07:35:03
品牌 Logo 应用领域
艾迪悌 - IDT 时钟
页数 文件大小 规格书
8页 69K
描述
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE

23S09E-1HPGGI8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:SOP,针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.67
系列:23S输入调节:MUX
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:16实输出次数:8
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
Same Edge Skew-Max(tskwd):0.25 ns最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
最小 fmax:200 MHzBase Number Matches:1

23S09E-1HPGGI8 数据手册

 浏览型号23S09E-1HPGGI8的Datasheet PDF文件第2页浏览型号23S09E-1HPGGI8的Datasheet PDF文件第3页浏览型号23S09E-1HPGGI8的Datasheet PDF文件第4页浏览型号23S09E-1HPGGI8的Datasheet PDF文件第5页浏览型号23S09E-1HPGGI8的Datasheet PDF文件第6页浏览型号23S09E-1HPGGI8的Datasheet PDF文件第7页 
IDT23S09E  
3.3V ZERO DELAY  
CLOCK BUFFER, SPREAD  
SPECTRUM COMPATIBLE  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 200MHz operating frequency  
• Distributes one clock input to one bank of five and one bank of  
four outputs  
The IDT23S09E is a high-speed phase-lock loop (PLL) clock buffer,  
designedtoaddresshigh-speedclockdistributionapplications. Thezero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 200MHz.  
• Separate output enable for each output bank  
• Output Skew < 250ps  
• Low jitter <200 ps cycle-to-cycle  
• IDT23S09E-1 for Standard Drive  
• IDT23S09E-1H for High Drive  
TheIDT23S09Eisa16-pinversionoftheIDT23S05E. TheIDT23S09E  
acceptsonereferenceinput,anddrivestwobanksoffourlowskewclocks.  
The-1Hversionofthisdeviceoperatesupto200MHzfrequencyandhas  
higher drive than the -1 device. All parts have on-chip PLLs which lock  
to an input clock on the REF pin. The PLL feedback is on-chip and is  
obtained from the CLKOUT pad. In the absence of an input clock, the  
IDT23S09E enters power down. In this mode, the device will draw less  
• No external RC network required  
• Operates at 3.3V VDD  
• Spread spectrum compatible  
• Available in SOIC and TSSOP packages  
than 12µA for Commercial Temperature range and less than 25µA for  
Industrial temperature range, and the outputs are tri-stated.  
The IDT23S09E is characterized for both Industrial and Commercial  
operation.  
FUNCTIONALBLOCKDIAGRAM  
16  
CLKOUT  
2
CLKA1  
PLL  
1
REF  
3
CLKA2  
14  
CLKA3  
15  
CLKA4  
8
S2  
Control  
Logic  
9
S1  
6
CLKB1  
7
CLKB2  
10  
CLKB3  
11  
CLKB4  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
MAY 2010  
1
c
2006 Integrated Device Technology, Inc.  
DSC - 6399/11  

23S09E-1HPGGI8 替代型号

型号 品牌 替代类型 描述 数据表
IDT23S09E-1HPGI8 IDT

完全替代

PLL Based Clock Driver, 23S Series, 9 True Output(s), 0 Inverted Output(s), PDSO16, TSSOP-
CY2309ZXC-1HT CYPRESS

类似代替

Low-Cost 3.3V Zero Delay Buffer
CY2309ZXC-1H CYPRESS

类似代替

Low-Cost 3.3V Zero Delay Buffer

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