Datasheet > 23S09T-1DCG8

23S09T-1DCG8

更新时间： 2024-11-18 12:20:39

品牌	Logo	应用领域
艾迪悌 - IDT		时钟
页数	文件大小	规格书
6页	61K
描述
2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE

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替代型号

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23S09T-1DCG8 数据手册

IDT23S09T

2.5VZERODELAYCLOCKBUFFER,SPREADSPECTRUMCOMPATIBLE

COMMERCIALTEMPERATURERANGE

IDT23S09T

2.5V ZERO DELAY

CLOCK BUFFER, SPREAD

SPECTRUM COMPATIBLE

FEATURES:

DESCRIPTION:

• Phase-Lock Loop Clock Distribution

• 10MHz to 133MHz operating frequency

• Distributes one clock input to one bank of five and one bank of

four outputs

The IDT23S09T is a high-speed phase-lock loop (PLL) clock buffer,

designedtoaddresshigh-speedclockdistributionapplications. Thezero

delay is achieved by aligning the phase between the incoming clock and

the output clock, operable within the range of 10 to 133MHz.

• Separate output enable for each output bank

• Output Skew < 250ps

• Low jitter <200 ps cycle-to-cycle

• No external RC network required

• Operates at 2.5V VDD

TheIDT23S09Tisa16-pinversionoftheIDT23S05T. TheIDT23S09T

acceptsonereferenceinput,anddrivestwobanksoffourlowskewclocks.

All parts have on-chip PLLs which lock to an input clock on the REF pin.

The PLL feedback is on-chip and is obtained from the CLKOUT pad. In

the absence of an input clock, the IDT23S09T enters power down, and

• Spread spectrum compatible

• Available in SOIC package

theoutputsaretri-stated.Inthismode,thedevicewilldrawlessthan12µA.

FUNCTIONALBLOCKDIAGRAM

CLKOUT

CLKA1

PLL

REF

CLKA2

CLKA3

CLKA4

Control

Logic

CLKB1

CLKB2

CLKB3

CLKB4

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL TEMPERATURE RANGE

MAY 2010

2003 Integrated Device Technology, Inc.

DSC 6396/8

12 3 4 5 6

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23S09T-1DCG8 替代型号

型号	品牌	替代类型	描述	数据表
IDT23S09T-1DC8	IDT	完全替代	PLL Based Clock Driver, 23S Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, SOIC-1
23S09T-1DCG	IDT	完全替代	2.5V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE
CY2309SXI-1H	CYPRESS	功能相似	Low-Cost 3.3V Zero Delay Buffer

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