Datasheet > 23S09-1HDCG8

23S09-1HDCG8

更新时间： 2022-09-15 17:49:12

品牌	Logo	应用领域
艾迪悌 - IDT		时钟
页数	文件大小	规格书
8页	69K
描述
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

23S09-1HDCG8 数据手册

IDT23S09

3.3VZERODELAYCLOCKBUFFER

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

ZERO DELAY AND SKEW CONTROL

All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative

loading can affect and adjust the input/output delay. The Output Load Difference diagram illustrates the PLL's relative loading with respect to the other

outputs that can adjust the Input-Output (I/O) Delay.

For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive

load equal to that on the other outputs in order to obtain true zero I/O Delay. For zero output-to-output skew, all outputs must be loaded equally.

SWITCHINGWAVEFORMS

1.4V

Output

1.4V

Output

Output to Output Skew

Duty Cycle Timing

VDD/2

3.3V

REF

0.8V

Output

VDD/2

Output

Input to Output Propagation Delay

All Outputs Rise/Fall Time

CLK

VDD/2

OUT

Device 1

CLK

OUT

Device 2 t7

VDD/2

Device to Device Skew

1...3 4 567 8

下载PDF

与23S09-1HDCG8相关器件

型号	品牌	描述	获取价格	数据表
23S09-1HDCGI	IDT	3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE	获取价格
23S09-1HDCGI8	IDT	3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE	获取价格
23S09-1HPGG	IDT	3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE	获取价格
23S09-1HPGG8	IDT	3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE	获取价格
23S09-1HPGGI	IDT	3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE	获取价格
23S09-1HPGGI8	IDT	3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE	获取价格