Datasheet > 23S09-1HDCG8

23S09-1HDCG8

更新时间： 2022-09-15 17:49:12

品牌	Logo	应用领域
艾迪悌 - IDT		时钟
页数	文件大小	规格书
8页	69K
描述
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE

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23S09-1HDCG8 数据手册

IDT23S09

3.3VZERODELAYCLOCKBUFFER

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

FUNCTIONTABLE⁽¹⁾

CLKA

Tri-State

Driven

CLKB

Tri-State

Driven

CLKOUT⁽²⁾

Driven

Output Source

PLL Shut Down

PLL

REF

Driven

PLL

NOTES:

1. H = HIGH Voltage Level.

L = LOW Voltage Level

2. This output is driven and has an internal feedback for the PLL. The load on this ouput can be adjusted to change the skew between the REF and the output.

DCELECTRICALCHARACTERISTICS-COMMERCIAL

Symbol

VIL

Parameter

Conditions

Min.

—

Max.

0.8

—

Unit

InputLOWVoltageLevel

Input HIGH Voltage Level

InputLOWCurrent

Input HIGH Current

OutputLOWVoltage

VIH

IIL

VIN = 0V

—

µA

IIH

VIN = VDD

100

0.4

VOL

StandardDrive

High Drive

StandardDrive

High Drive

IOL = 8mA

IOL = 12mA (-1H)

IOH = -8mA

VOH

Output HIGH Voltage

2.4

—

IOH = -12mA (-1H)

IDD_PD

IDD

Power Down Current

SupplyCurrent

REF = 0MHz (S2 = S1 = H)

Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND

—

µA

OPERATINGCONDITIONS-COMMERCIAL

Symbol

Parameter

Min.

Max.

3.6

Unit

VDD

SupplyVoltage

OperatingTemperature(AmbientTemperature)

Load Capacitance < 100MHz

°C

—

Load Capacitance 100MHz - 133MHz

InputCapacitance

CIN

SWITCHINGCHARACTERISTICS(23S09-1)-COMMERCIAL^(1,2)

Symbol

Parameter

Conditions

Min.

—

Typ.

—

Max.

Unit

OutputFrequency

10pFLoad

30pFLoad

133

100

MHz

Duty Cycle = t2 ÷ t1

RiseTime

Measured at 1.4V, FOUT = 66.66MHz

Measured between 0.8V and 2V

Alloutputsequallyloaded

2.5

250

350

8.7

700

200

FallTime

OutputtoOutputSkew

Delay, REF Rising Edge to CLKOUT Rising Edge⁽²⁾MeasuredatVDD/2

Delay, REF Rising Edge to CLKOUT Rising Edge⁽²⁾Measured at VDD/2 in PLL bypass mode (IDT23S09 only)

t6A

t6B

Device-to-Device Skew

Cycle-to-Cycle Jitter

Measured at VDD/2 on the CLKOUT pins of devices

Measuredat66.66MHz,loadedoutputs

—

tLOCK PLLLockTime

Stable power supply, valid clock presented on REF pin

—

NOTES:

1. REF Input has a threshold voltage of VDD/2.

2. All parameters specified with loaded outputs.

1 234 5 6 7 8

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