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20P60 PDF预览

20P60

更新时间: 2024-11-01 00:04:27
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA
页数 文件大小 规格书
12页 265K
描述
P-Channel Enhancement-Mode Silicon Gate

20P60 数据手册

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Order this document  
by MTD20P06HDL/D  
SEMICONDUCTOR TECHNICAL DATA  
Motorola Preferred Device  
TMOS POWER FET  
LOGIC LEVEL  
15 AMPERES  
60 VOLTS  
P–Channel Enhancement–Mode Silicon Gate  
This advanced high–cell density HDTMOS E–FET is designed to  
withstand high energy in the avalanche and commutation modes.  
The new energy efficient design also offers a drain–to–source  
diode with a fast recovery time. Designed for low–voltage,  
high–speed switching applications in power supplies, converters  
and PWM motor controls, and other inductive loads. The avalanche  
energy capability is specified to eliminate the guesswork in designs  
where inductive loads are switched, and to offer additional safety  
margin against unexpected voltage transients.  
R
= 175 M  
DS(on)  
D
Ultra Low R , High–Cell Density, HDTMOS  
DS(on)  
Diode is Characterized for Use in Bridge Circuits  
and V Specified at Elevated Temperature  
I
DSS  
DS(on)  
G
Avalanche Energy Specified  
CASE 369A–13, Style 2  
DPAK  
Surface Mount Package Available in 16 mm, 13–inch/2500  
Unit, Tape & Reel, Add T4 Suffix to Part Number  
S
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
C
Rating  
Symbol  
Value  
60  
Unit  
Drain–Source Voltage  
V
DSS  
Vdc  
Vdc  
Drain–Gate Voltage (R  
= 1.0 M)  
Gate–Source Voltage — Continuous  
V
DGR  
60  
GS  
V
± 15  
± 20  
Vdc  
Vpk  
GS  
Gate–Source Voltage — Non–Repetitive (t 10 ms)  
V
GSM  
p
Drain Current — Continuous  
Drain Current — Continuous @ 100°C  
Drain Current — Single Pulse (t 10 µs)  
I
I
15  
9.0  
45  
Adc  
Apk  
D
D
I
p
DM  
Total Power Dissipation  
Derate above 25°C  
Total Power Dissipation @ T = 25°C (1)  
P
D
72  
0.58  
1.75  
Watts  
W/°C  
Watts  
C
Operating and Storage Temperature Range  
T , T  
stg  
55 to 150  
300  
°C  
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C  
E
AS  
mJ  
J
(V  
DD  
= 25 Vdc, V = 5.0 Vdc, I = 15 Apk, L = 2.7 mH, R = 25 )  
GS L G  
Thermal Resistance — Junction to Case  
Thermal Resistance — Junction to Ambient  
Thermal Resistance — Junction to Ambient (1)  
R
R
R
1.73  
100  
71.4  
°C/W  
°C  
θJC  
θJA  
θJA  
Maximum Temperature for Soldering Purposes, 1/8from case for 10 seconds  
(1) When surface mounted to an FR4 board using the minimum recommended pad size.  
T
260  
L
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit  
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.  
Designer’s, E–FET and HDTMOS are trademarks of Motorola Inc.  
TMOS is a registered trademark of Motorola Inc.  
Thermal Clad is a trademark of the Bergquist Company.  
Preferred devices are Motorola recommended choices for future use and best overall value.  
REV 1  
Motorola, Inc. 1995  

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