Datasheet > 1892YLFT

1892YLFT

更新时间： 2024-11-11 19:56:59

品牌	Logo	应用领域
艾迪悌 - IDT		通信时钟数据传输外围集成电路
页数	文件大小	规格书
148页	663K
描述
Serial I/O Controller, 1 Channel(s), 12.5MBps, CMOS, PQFP64, 14 X 14 MM, ROHS COMPLIANT, MQFP-64

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1892YLFT 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFP,	针数：	64
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.82	地址总线宽度：
边界扫描：	NO	最大时钟频率：	25 MHz
通信协议：	SYNC, BYTE	数据编码/解码方法：	NRZ; NRZI; BIPH-LEVEL(MANCHESTER)
最大数据传输速率：	12.5 MBps	外部数据总线宽度：
JESD-30 代码：	S-PQFP-G64	长度：	14 mm
低功率模式：	YES	串行 I/O 数：	1
端子数量：	64	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装形状：	SQUARE
封装形式：	FLATPACK	认证状态：	Not Qualified
座面最大高度：	3 mm	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
宽度：	14 mm	uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches：	1

1892YLFT 数据手册

Integrated Circuit Systems, Inc.

Document Type: Data Sheet

Document Stage: Released

ICS1892

10Base-T/100Base-TX Integrated PHYceiver

General

Features

The ICS1892, an enhanced version of the ICS 1890, is a

fully integrated, physical-layer device (PHY) that is

compliant with both the 10Base-T and 100Base-TX

CSMA/CD Ethernet Standard, ISO/IEC 8802-3.

• Supports category 5 cables with attenuation in excess of

24 dB at 100 MHz across a temperature range from -5° to

+85° C

• DSP-based baseline wander correction to virtually

eliminate killer packets across temperature range of from

-5° to +85° C

The ICS1892 incorporates digital signal processing (DSP)

in its Physical Medium Dependent (PMD) sublayer. As a

result, it can transmit and receive data on unshielded

twisted-pair (UTP) category 5 cable with attenuation in

excess of 24 dB at 100 MHz. With this ICS-patented

technology, the ICS1892 can virtually eliminate errors from

killer packets.

• Low-power, 0.5-micron CMOS

• Single 5.0-V power supply.

• Single-chip, fully integrated PHY provides PCS, PMA,

PMD, and AUTONEG sublayers of IEEE standard

• 10Base-T and 100Base-TX IEEE 802.3 compliant

• Fully integrated, DSP-based PMD includes:

– Adaptive equalization and baseline wander correction

– Transmit wave shaping and stream cipher scrambler

– MLT-3 encoder and NRZ/NRZI encoder

The ICS1892 supports a broad range of applications: data

terminal equipment (network interface cards and

motherboards), switches, repeaters, bridges, and routers. Its

Media Independent Interface (MII) supports direct

chip-to-chip and motherboard-to-daughterboard

connections as well as connections to an MII connector and

cable. The ICS1892 also provides a Serial Management

Interface for exchanging command and status information

with a Station Management (STA) entity.

• Highly configurable design supports:

– Node, repeater, and switch applications

– Managed and unmanaged applications

– 10M or 100M half- and full-duplex modes

– Parallel detection

– Auto-negotiation, with Next Page capabilities

The ICS1892 Media Dependent Interface (MDI) can be

configured to provide either half- or full-duplex operation at

data rates of 10 MHz or 100 MHz. The MDI configuration

can be done manually (with input pins or control register

settings) or automatically (using the Auto-Negotiation

features). When the ICS1892 Auto-Negotiation sublayer is

enabled, it exchanges technology capability data with its

remote link partner and automatically selects the

highest-performance operating mode they have in common.

• MAC/Repeater Interface can be configured as:

– 10M or 100M Media Independent Interface

– 100M Symbol Interface (bypasses the PCS)

– 10M 7-wire Serial Interface

• Provides Loopback Modes for Diagnostic Functions

• Small Footprint 64-pin Low-Profile LQFP and MQFP

packages available

ICS1892 Block Diagram

100Base-T

PCS

•

Frame

CRS/COL

Detection

10/100 MII or

Alternate

MAC/Repeater

Interface

Twisted-

Pair

Interface to

Magnetics

Modules and

RJ45

Interface

MUX

Integrated

Switch

•

Parallel to Serial

4B/5B

10Base-T

Connector

MII

Low-Jitter

Clock

Synthesizer

Auto-

Negotiation

Configuration

and Status

Extended

Set

MII Serial

Management

Interface

Clock

Power

LEDs and PHY

Address

1892 Rev. D, 2/26/01

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any information

being relied upon by the customer is current and accurate.

12 3 4 5 6 7...148

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