Datasheet > 17512LJC

17512LJC

更新时间： 2024-11-07 23:13:23

品牌	Logo	应用领域
赛灵思 - XILINX		可编程只读存储器
页数	文件大小	规格书
10页	73K
描述
Serial Configuration PROMs

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数据手册

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17512LJC 数据手册

XC1701L (3.3V), XC1701 (5.0V) and

XC17512L (3.3V)

Serial Conﬁguration PROMs

December 10, 1997 (Version 1.1)

Product Specification

Features

Description

•

On-chip address counter, incremented by each rising

edge on the clock input

Simple interface to the FPGA; requires only one user

I/O pin

Cascadable for storing longer or multiple bitstreams

Programmable reset polarity (active High or active Low)

for compatibility with different FPGA solutions

Supports XC4000EX/XL fast conﬁguration mode (15.0

MHz)

Low-power CMOS Floating Gate process

Available in 5 V and 3.3 V versions

Available in compact plastic packages: 8-pin PDIP,

20-pin SOIC, and 20-pin PLCC.

The XC1701L, XC1701 and XC17512L serial conﬁguration

PROMs (SCPs) provide an easy-to-use, cost-effective

method for storing Xilinx FPGA conﬁguration bitstreams.

•

When the FPGA is in master serial mode, it generates a

conﬁguration clock that drives the SCP. A short access time

after the rising clock edge, data appears on the SCP DATA

output pin that is connected to the FPGA DIN pin. The

FPGA generates the appropriate number of clock pulses to

complete the conﬁguration. Once conﬁgured, it disables the

SCP. When the FPGA is in slave mode, the SCP and the

FPGA must both be clocked by an incoming signal.

•

Multiple devices can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all SCPs in this chain

are interconnected. All devices are compatible and can be

cascaded with other members of the family.

•

Programming support by leading programmer

manufacturers.

Design support using the Xilinx Alliance and

Foundation series software packages.

For device programming, either the Xilinx Alliance or Foun-

dation series development system compiles the FPGA

design ﬁle into a standard Hex format, which is then trans-

ferred to the programmer.

GND

CEO

RESET/

OE or

OE/

RESET

Address Counter

CLK

EPROM

Cell

Output

DATA

Matrix

X3185

Figure 1: Simpliﬁed Block Diagram (does not show programming circuit)

December 10, 1997 (Version 1.1)

5-1

12 3 4 5 6 7...10

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