Datasheet > 10M50DCF484C8G

10M50DCF484C8G

更新时间： 2023-04-15 00:00:00

品牌	Logo	应用领域
英特尔 - INTEL		栅
页数	文件大小	规格书
68页	976K
描述
Field Programmable Gate Array, 50000-Cell, CMOS, PBGA484, 23 X 23 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-484

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

10M50DCF484C8G 数据手册

M10-DATASHEET

2015.05.04

Document Revision History for MAX 10 FPGA Device Datasheet

Date

Version

Changes

•

Updated t_{x Jitter}specifications in the following tables:

•

True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply

Devices

•

True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for MAX 10 Dual Supply

Devices

•

Emulated RSDS_E_1R Transmitter Timing Specifications for MAX 10 Dual Supply Devices

True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for MAX 10 Dual

Supply Devices

•

True LVDS Transmitter Timing Specifications for MAX 10 Dual Supply Devices

Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for MAX 10 Dual

Supply Devices

•

Updated SW specifications in LVDS Receiver Timing Specifications for MAX 10 Single Supply Devices

table.

Added a note to t_{x Jitter}for all LVDS tables. Note: TX jitter is the jitter induced from core noise and I/O

switching noise.

Updated the description for t_LOCKfor all LVDS tables: Time required for the PLL to lock, after CONF_DONE

signal goes high, indicating the completion of device configuration.

Updated Memory Output Clock Jitter Specifications section.

•

Updated maximum external memory interfaces frequency from 300 MHz to 303 MHz.

Updated PLL output routing from global clock network to PHY clock network.

•

Added I/O Timing for MAX 10 Devices table.

Added V_HYSin the Glossary table.

January 2015

2015.01.23

•

Removed a note to V_CCAin Power Supplies Recommended Operating Conditions for MAX 10 Dual Supply

Devices table. This note is not valid: All V_CCApins must be connected together for EQFP package.

Corrected the maximum value for t_{OUTJITTER_CCJ_ IO}(F_OUT≥ 100 MHz) from 60 ps to 650 ps in PLL Specifi‐

cations for MAX 10 Devices table.

MAX 10 FPGA Device Datasheet

Send Feedback

Altera Corporation

1...63 64 656667 68

下载PDF

与10M50DCF484C8G相关器件

型号	品牌	描述	获取价格	数据表
10M50DFF672I7G	INTEL	Field Programmable Gate Array, 50000-Cell, CMOS, PBGA672, 27 X 27 MM, 1 MM PITCH, ROHS COM	获取价格
10M50SAE144I7G	INTEL	Field Programmable Gate Array, PQFP144, 22 X 22 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC	获取价格
10M7.5D	EUROQUARTZ	Crystal Filter,	获取价格
10M7A	VANLONG	Monolithic Crystal Filters (MCFs)	获取价格
10M7A	FOX	Crystal Filter, 1 Function(s), 10.7MHz, 3.75kHz BW(delta f), Monolithic	获取价格
10M7B	VANLONG	Monolithic Crystal Filters (MCFs)	获取价格