Datasheet > 10M50DCF484C8G

10M50DCF484C8G

更新时间： 2023-04-15 00:00:00

品牌	Logo	应用领域
英特尔 - INTEL		栅
页数	文件大小	规格书
68页	976K
描述
Field Programmable Gate Array, 50000-Cell, CMOS, PBGA484, 23 X 23 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-484

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10M50DCF484C8G 数据手册

M10-DATASHEET

2015.05.04

Document Revision History for MAX 10 FPGA Device Datasheet

Date

Version

Changes

•

Added specifications for low-speed I/O performance pin sampling window in LVDS Receiver Timing

Specifications for MAX 10 Single Supply Devices table: Max = 900 ps for –C7, –I7, –A7, and –C8 speed

grades.

•

Added t_{RU_nCONFIG}and t_{RU_nRSTIMER}specifications for different devices in Remote System Upgrade

Circuitry Timing Specifications for MAX 10 Devices table.

Removed the word "internal oscillator" in User Watchdog Timer Specifications for MAX 10 Devices table to

avoid confusion.

Added IOE programmable delay specifications.

September 2014

2014.09.22 Initial release.

MAX 10 FPGA Device Datasheet

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