Datasheet > 10M50DCF484A7G

10M50DCF484A7G

更新时间： 2023-06-15 00:00:00

品牌	Logo	应用领域
英特尔 - INTEL		栅
页数	文件大小	规格书
14页	604K
描述
Field Programmable Gate Array, PBGA484, 23 X 23 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-484

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10M50DCF484A7G 数据手册

M10-OVERVIEW

2014.09.22

Configuration

External Memory Interface⁽²⁾

I/O Standard

SSTL-18

Maximum Width

16 bit + 8 bit ECC

16 bit without ECC

Maximum Frequency (MHz)

DDR2 SDRAM

200

LPDDR2 SDRAM

HSUL-12

Note: MAX 10 FPGA support for the DDR3, DDR3L, DDR2, and LPDDR2 external memory interfaces is

not available by default in the Quartus II software. Contact your local sales representative for

support.

Related Information

External Memory Interface Spec Estimator

Provides a parametric tool that allows you to find and compare the performance of the supported external

memory interfaces in Altera devices.

Configuration

Table 12: Configuration Features

Feature

Description

Dual-image configuration

•

Stores two configuration images in the configuration flash memory

(CFM)

Selects the first configuration image to boot using the BOOT_SEL

Design security

•

Supports 128 bit key with non-volatile key programming

Limits access of the JTAG instruction during power-up in the JTAG

secure mode

SEU Mitigation⁽³⁾

•

Auto-detects cyclic redundancy check (CRC) errors during configu‐

ration

Provides optional CRC error detection and identification in user

mode.

Dual-purpose configuration pin

Configuration data compression

•

Functions as configuration pins prior to user mode

Provides option to be used as configuration pins or user I/O pins in

user mode

•

Receives compressed configuration bitstream and decompresses the

data in real-time during configuration

Reduces the configuration image size stored in the CFM

(2)

The device hardware supports SRAM. Use your own design to interface with SRAM devices.

The SEU mitigation feature for single supply devices is disabled by default in the Quartus II software. For

more information and support, contact your local sales representative.

(3)

MAX 10 FPGA Device Overview

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