Datasheet > 10M50DCF484A7G

10M50DCF484A7G

更新时间： 2023-06-15 00:00:00

品牌	Logo	应用领域
英特尔 - INTEL		栅
页数	文件大小	规格书
14页	604K
描述
Field Programmable Gate Array, PBGA484, 23 X 23 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-484

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数据手册

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10M50DCF484A7G 数据手册

M10-OVERVIEW

2014.09.22

Analog-to-Digital Converter

Figure 4: MAX 10 Device Family LEs

Routing from

previous LE

LAB-Wide

Synchronous

Load

LAB-Wide

Synchronous

Clear

ammable

Progr

Regist

LE Carry-In

data 1

Row, Column,

And Direct Link

Routing

data 2

data 3

Synchronous

Load and

Clear Logic

Carry

Chain

Look-Up Table

(LUT)

data 4

ENA

CLRN

Row, Column,

And Direct Link

Routing

labclr1

labclr2

Asynchronous

Clear Logic

Chip-Wide

Reset

(DEV_CLRn)

Local

Routing

Clock &

Clock Enable

Select

Output

labclk1

labclk2

LE Carry-Out

labclkena1

labclkena2

Analog-to-Digital Converter

MAX 10 devices feature up to two analog-to-digital converters (ADC). The ADCs of the MAX 10 devices

monitor the internal temperature of the die and support external analog signal conversion.

Table 8: ADC Features

Feature

Description

12 bits resolution

•

Translates analog quantities to digital data for informa‐

tion processing, computing, data transmission, and

control systems

Provides a 12 bit digital representation of the observed

analog signal

Up to 1 MSPS sampling rate

Monitors single-ended external inputs with a cumulative

sampling rate of 1 MSPS in normal mode

MAX 10 FPGA Device Overview

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Altera Corporation

1...6 7 8910 11 12...14

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