Datasheet > 10M50DCF484A7G

10M50DCF484A7G

更新时间： 2023-06-15 00:00:00

品牌	Logo	应用领域
英特尔 - INTEL		栅
页数	文件大小	规格书
14页	604K
描述
Field Programmable Gate Array, PBGA484, 23 X 23 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-484

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10M50DCF484A7G 数据手册

M10-OVERVIEW

2014.09.22

Embedded Memory Blocks

•

DSP IP cores:

•

Common DSP processing functions such as finite impulse response (FIR), fast Fourier transform

(FFT), and numerically controlled oscillator (NCO) functions

•

Suites of common video and image processing functions

•

Complete reference designs for end-market applications

DSP Builder interface tool between the Quartus II software and the MathWorks Simulink and

MATLAB design environments

•

DSP development kits

Embedded Memory Blocks

Each M9K memory block of the MAX 10 device provides 9 Kb of on-chip memory capable of operating at

up to 284 MHz. The embedded memory structure consists of M9K memory blocks columns. You can

configure the columns of the embedded M9K memory blocks as either one of the following:

•

RAM

First-in first-out (FIFO) buffers

ROM

The MAX 10 device memory blocks are optimized for applications such as high throughput packet

processing, embedded processor program, and embedded data storage.

You can utilize the M9K memory blocks using the following options:

•

Parameterize relevant IP cores with the Quartus II parameter editor

Infer the multipliers directly with VHDL or Verilog

Table 10: M9K Supported Operation Modes and Configurations

M9K Operation Modes

Port Widths Configuration

Single-port

×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36

×1, ×2, ×4, ×8, ×9, ×16, and ×18

Simple dual-port

True dual-port

Clocking and PLL

MAX 10 devices support up to 20 global clock (GCLK) networks with operating frequency up to

450 MHz. The GCLK networks have high drive strength and low skew.

MAX 10 devices have built-in internal oscillator.

The high precision and low jitter PLLs have the following usages:

MAX 10 FPGA Device Overview

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