100336FC

更新时间： 2024-10-28 13:03:11

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		移位寄存器计数器
页数	文件大小	规格书
14页	152K
描述
Binary Counter, 100K Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, ECL, CQFP24, CERPACK-24

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100336FC 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFF,	针数：	24
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.38	其他特性：	CAN BE USED AS 4-BIT BIDIRECTIONAL SHIFT REGISTER
计数方向：	BIDIRECTIONAL	系列：	100K
JESD-30 代码：	S-GQFP-F24	长度：	9.398 mm
负载/预设输入：	YES	逻辑集成电路类型：	BINARY COUNTER
工作模式：	SYNCHRONOUS	位数：	4
功能数量：	1	端子数量：	24
最高工作温度：	85 °C	最低工作温度：
输出特性：	OPEN-EMITTER	封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	QFF	封装形状：	SQUARE
封装形式：	FLATPACK	传播延迟（tpd）：	1.8 ns
认证状态：	Not Qualified	座面最大高度：	2.159 mm
表面贴装：	YES	技术：	ECL
温度等级：	OTHER	端子形式：	FLAT
端子节距：	1.27 mm	端子位置：	QUAD
触发器类型：	POSITIVE EDGE	宽度：	9.398 mm
最小 fmax：	350 MHz	Base Number Matches：	1

100336FC 数据手册

August 1989

Revised August 2000

100336

Low Power 4-Stage Counter/Shift Register

vidual Preset (P_n) inputs are used to enter data in parallel

General Description

The 100336 operates as either a modulo-16 up/down

counter or as a 4-bit bidirectional shift register. Three

Select (S_n) inputs determine the mode of operation, as

or to preset the counter in programmable counter applica-

tions. A HIGH signal on the Master Reset (MR) input over-

rides all other inputs and asynchronously clears the flip-

flops. In addition, a synchronous clear is provided, as well

as a complement function which synchronously inverts the

contents of the flip-flops. All inputs have 50 kΩ pull-down

resistors.

shown in the Function Select table. Two Count Enable

(CEP, CET) inputs are provided for ease of cascading in

multistage counters. One Count Enable (CET) input also

doubles as a Serial Data (D₀) input for shift-up operation.

For shift-down operation, D₃is the Serial Data input. In

Features

counting operations the Terminal Count (TC) output goes

LOW when the counter reaches 15 in the count/up mode or

0 (zero) in the count/down mode. In the shift modes, the TC

output repeats the Q₃output. The dual nature of this TC/Q₃

■ 40% power reduction of the 100136

■ 2000V ESD protection

■ Pin/function compatible with 100136

■ Voltage compensated operating range = −4.2V to −5.7V

■ Available to industrial grade temperature range

output and the D₀/CET input means that one interconnec-

tion from one stage to the next higher stage serves as the

link for multistage counting or shift-up operation. The indi-

Ordering Code:

Order Number Package Number

Package Description

100336SC

100336PC

100336QC

100336QI

M24B

N24E

V28A

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (−40°C to +85°C)

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

24-Pin DIP/SOIC

28-Pin PLCC

Logic Symbol

DS010584

www.fairchildsemi.com

12 3 4 5 6 7...14

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与100336FC相关器件

型号	品牌	获取价格	描述	数据表
100336FCQR	ETC	获取价格	Counter/Shift Register
100336FM	ETC	获取价格	Counter/Shift Register
100336FMQB	ETC	获取价格	Counter/Shift Register
100336J-QMLV	ETC	获取价格	Counter/Shift Register
100336PC	FAIRCHILD	获取价格	Low Power 4-Stage Counter/Shift Register
100336QC	FAIRCHILD	获取价格	Low Power 4-Stage Counter/Shift Register
100336QC	TI	获取价格	100K SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PQCC28, PLAST
100336QC_NL	FAIRCHILD	获取价格	Binary Counter, 100K Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, E
100336QCQR	TI	获取价格	100K SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PQCC28, PLAST
100336QCX	FAIRCHILD	获取价格	Counter/Shift Register

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