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100331QI PDF预览

100331QI

更新时间: 2024-11-19 22:37:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路输入元件
页数 文件大小 规格书
10页 103K
描述
Low Power Triple D-Type Flip-Flop

100331QI 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:LCC包装说明:0.450 X 0.450 INCH, PLASTIC, MO-047, LCC-28
针数:28Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.56
Is Samacsys:N其他特性:WITH ADDITIONAL COMMON CLOCK; SET AND RESET INPUTS
系列:100KJESD-30 代码:S-PQCC-J28
JESD-609代码:e3长度:11.43 mm
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:375000000 Hz
湿度敏感等级:2位数:1
功能数量:3端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:OPEN-EMITTER输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):235
电源:-4.5 V最大电源电流(ICC):122 mA
Prop。Delay @ Nom-Sup:1.8 ns传播延迟(tpd):1.8 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:FF/Latches表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:11.43 mm最小 fmax:400 MHz
Base Number Matches:1

100331QI 数据手册

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February 1990  
Revised August 2000  
100331  
Low Power Triple D-Type Flip-Flop  
General Description  
The 100331 contains three D-type, edge-triggered master/  
slave flip-flops with true and complement outputs, a Com-  
mon Clock (CPC), and Master Set (MS) and Master Reset  
Features  
35% power reduction of the 100131  
2000V ESD protection  
Pin/function compatible with 100131  
(MR) inputs. Each flip-flop has individual Clock (CPn),  
Direct Set (SDn) and Direct Clear (CDn) inputs. Data enters  
a master when both CPn and CPC are LOW and transfers  
to a slave when CPn or CPC (or both) go HIGH. The Master  
Set, Master Reset and individual CDn and SDn inputs over-  
Voltage compensated operating range = −4.2V to 5.7V  
Available to industrial grade temperature range  
ride the Clock inputs. All inputs have 50 kpull-down  
resistors.  
Ordering Code:  
Order Number Package Number  
Package Description  
100331SC  
100331PC  
100331QC  
100331QI  
M24B  
N24E  
V28A  
V28A  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide  
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square  
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square  
Industrial Temperature Range (40°C to +85°C)  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagrams  
24-Pin DIP/SOIC  
Pin Descriptions  
Pin Names  
Description  
Individual Clock Inputs  
Common Clock Input  
28-Pin PLCC  
CP0CP2  
CPC  
D0D2  
CD0CD2  
SDn  
Data Inputs  
Individual Direct Clear Inputs  
Individual Direct Set Inputs  
Master Reset Input  
Master Set Input  
MR  
MS  
Q0-Q2  
Q0Q2  
Data Outputs  
Complementary Data Outputs  
© 2000 Fairchild Semiconductor Corporation  
DS010262  
www.fairchildsemi.com  

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