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06033J220GBS PDF预览

06033J220GBS

更新时间： 2024-10-31 01:16:31
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恩智浦 - NXP /
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19页 904K
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RF LDMOS Wideband Integrated Power Amplifier

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Document Number: MHV5IC2215N  
Rev. 3, 1/2007  
Freescale Semiconductor  
Technical Data  
RF LDMOS Wideband Integrated  
Power Amplifier  
The MHV5IC2215NR2 wideband integrated circuit is designed for base  
station applications. It uses Freescale’s High Voltage (28 Volts) LDMOS IC  
technology and integrates a two-stage structure. Its wideband on-chip  
matching design makes it usable from 1500 to 2200 MHz. The linearity  
performances cover all modulation formats for cellular applications including  
TD-SCDMA.  
MHV5IC2215NR2  
2170 MHz, 23 dBm, 28 V  
SINGLE N-CDMA, SINGLE W-CDMA  
RF LDMOS WIDEBAND  
Driver Application  
• Typical Single-Carrier N-CDMA Performance: VDD = 28 Volts, IDQ1  
=
164 mA, IDQ2 = 115 mA, Pout = 23 dBm, Full Frequency Band (1930-  
1990 MHz), IS-95 CDMA (Pilot, Sync, Paging, Traffic Codes 8 Through  
13) Channel Bandwidth = 1.2288 MHz. PAR = 9.8 dB @ 0.01%  
Probability on CCDF.  
INTEGRATED POWER AMPLIFIER  
Power Gain — 27.5 dB  
ACPR @ 885 kHz Offset — -60 dBc in 30 kHz Bandwidth  
16  
• Typical Single-Carrier W-CDMA Performance: VDD = 28 Volts, IDQ1  
=
1
164 mA, IDQ2 = 115 mA, Pout = 23 dBm, Full Frequency Band (2130-  
2170 MHz), Channel Bandwidth = 3.84 MHz, PAR = 8.5 dB @ 0.01%  
Probability on CCDF.  
CASE 978-03  
PFP-16  
Power Gain — 24 dB  
ACPR @ 5 MHz Offset — -55 dBc in 3.84 MHz Channel Bandwidth  
• Capable of Handling 3:1 VSWR, @ 28 Vdc, 2170 MHz, 15 Watts CW  
Output Power  
• Characterized with Series Equivalent Large-Signal Impedance Parameters  
and Common Source Scattering Parameters  
Features  
• On-Chip Matching (50 Ohm Input, >5 Ohm Output)  
• Integrated Quiescent Current Temperature Compensation  
with Enable/Disable Function  
• On-Chip Current Mirror gm Reference FET for Self Biasing Application (1)  
• Integrated ESD Protection  
• RoHS Compliant  
• In Tape and Reel. R2 Suffix = 1,500 Units per 16 mm, 13 inch Reel  
V
V
RD1  
N.C.  
1
2
3
4
N.C.  
V
16  
15  
14  
13  
RG1  
/RF  
/RF  
/RF  
/RF  
/RF  
V
DS2  
out  
out  
out  
out  
out  
RD1  
RG1  
V
V
V
V
V
DS2  
DS2  
DS2  
DS2  
V
DS1  
2 Stage IC  
V
DS1  
GND  
5
6
7
8
12  
11  
10  
9
RF  
V
/RF  
DS2 out  
in  
RF  
in  
V
V
/RF  
DS2 out  
GS1  
N.C.  
V
GS2  
V
V
GS1  
GS2  
Quiescent Current  
Temperature Compensation  
(Top View)  
Note: Exposed backside flag is source  
terminal for transistors.  
Figure 1. Block Diagram  
Figure 2. Pin Connections  
1. Refer to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to http://www.freescale.com/rf.  
Select Documentation/Application Notes - AN1987.  
© Freescale Semiconductor, Inc., 2007. All rights reserved.  
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