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ZL8101ALAFTK PDF预览

ZL8101ALAFTK

更新时间: 2024-11-30 01:14:39
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
36页 1573K
描述
Adaptive Digital DC/DC PWM Controller with Auto Compensation

ZL8101ALAFTK 数据手册

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DATASHEET  
ZL8101  
FN7832  
Rev 1.00  
July 13, 2012  
Adaptive Digital DC/DC PWM Controller with Auto Compensation  
The ZL8101 is a digital PWM controller with auto  
Features  
compensation that is designed to work with either the ZL1505  
MOSFET driver IC, ISL6611 Phase Doubler IC, or DrMOS type  
devices. Current sharing allows multiple devices to be  
connected in parallel to source loads with very high current  
demands. Adaptive performance optimization algorithms  
improve power conversion efficiency across the entire load  
range. Zilker Labs Digital-DC™ technology enables a blend of  
power conversion performance and power management  
features.  
• Efficient Synchronous Buck Controller  
• Adaptive Performance Optimization Algorithms  
• ±1% Output Voltage Accuracy  
• Auto Compensation  
Snapshot™ Parametric Capture  
• I2C/SMBus Interface, PMBus Compatible  
• Internal Non-Volatile Memory (NVM)  
• Tri-State PWM Gate Outputs  
The ZL8101 is designed to be a flexible building block for DC  
power and can be easily adapted to designs ranging from a  
single-phase power supply operating from a 4.5V input to a  
multi-phase supply operating from a 12V input. The ZL8101  
eliminates the need for complicated power supply managers  
as well as numerous external discrete components.  
• Compatible with Industry Standard DrMOS Devices  
• Compatible with Intersil ISL6611 Phase Doubler  
• Synchronized External Driver Control  
Most operating features can be configured by simple  
pin-strap/resistor selection or through the SMBus™ serial  
interface. The ZL8101 uses the PMBus™ protocol for  
communication with a host controller and the Digital-DC bus  
for communication between other Zilker Labs devices.  
Applications  
• Servers/Storage Equipment  
• Telecom/Datacom Equipment  
• Power Supplies (Memory, DSP, ASIC, FPGA)  
Related Literature  
AN2033 “Zilker Labs PMBus Command Set - DDC Products”  
AN2034 “Configuring Current Sharing on the ZL2004 and  
ZL2006”  
AN2010 “Thermal and Layout Guidelines for Digital-DC™  
Products”  
96  
V
= 3.3V  
OUT  
91  
V
= 1.5V  
OUT  
V
= 1.0V  
OUT  
V
= 1.8V  
86  
81  
76  
OUT  
V
= 1.2V  
OUT  
V
= 2.5V  
OUT  
V
= 12V  
IN  
f
= 400kHz  
SW  
L = 0.45µH  
G
= 1 x BSC050NE2Ls  
H
L
G
= 2 x BSC010NE2LS  
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40  
OUTPUT CURRENT (A)  
FIGURE 1. EFFICIENCY vs LOAD CURRENT  
FN7832 Rev 1.00  
July 13, 2012  
Page 1 of 36  

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