ZL50073GA

更新时间： 2024-01-29 11:03:07

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		开关
页数	文件大小	规格书
67页	612K
描述
Digital Time Switch, PBGA484, 23 X 23 MM, 1 MM PITCH, PLASTIC, BGA-484

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技术参数
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ZL50073GA 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	BGA,	针数：	484
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.53	JESD-30 代码：	S-PBGA-B484
JESD-609代码：	e0	长度：	23 mm
功能数量：	1	端子数量：	484
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	225	认证状态：	Not Qualified
座面最大高度：	2.16 mm	标称供电电压：	1.8 V
表面贴装：	YES	电信集成电路类型：	DIGITAL TIME SWITCH
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	23 mm	Base Number Matches：	1

ZL50073GA 数据手册

ZL50073

Data Sheet

Applications

•

Large Switching Platforms

Central Office Switches

Wireless Base Stations

Multi-service Access Platforms

Media Gateways

Description

The ZL50073 is a non-blocking Time Division Multiplex (TDM) switch with maximum 32,768 x 32,768 channels. The

device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. With a

number of enhanced features, the ZL50073 is designed for high capacity voice and data switching applications.

The ZL50073 has 128 input and 128 output data streams which can operate at 8.192 Mbps, 16.384 Mbps,

32.768 Mbps or 65.536 Mbps. The large number of inputs and outputs maintains full 32 K x 32 K channel switching

capacity at bit rates of 65 Mbps, 32 Mbps and 16 Mbps. Up to 32 input and output data streams may operate at

65 Mbps. Up to 64 input and output data streams may operate at 32 Mbps. Up to 128 input and output data streams

may operate at 16 Mbps or 8 Mbps. The data rate can be independently set in groups of 4 input or output streams.

In this way it is possible to provide rate conversion from input data channel to output data channel.

The ZL50073 uses a master clock (CKi0) and frame pulse (FPi0) to define the TDM data stream frame boundary

and timing. A high speed system clock is derived internally from CKi0 and FPi0. The input and output data streams

can independently reference their timings to one of the input clocks or to the internal system clock.

The ZL50073 has a variety of user configurable options designed to provide flexibility when data streams are

connected to multiple TDM components or circuits. These include:

•

Two additional programmable reference inputs, CKi2 - 1 and FPi2 - 1, which can be used to provide

alternative sources for input and output stream timing

Variable input bit delay and output advancement, to accommodate delays and frame offsets of streams

connected through different data paths

Four timing outputs, CKo3 - 0 and FPo3 - 0, which can be configured independently to provide a variety of

clock and frame pulse options

Support of both ST-BUS and GCI-Bus formats

The ZL50073 also has a number of value added features for voice and data applications:

•

Per-channel variable delay mode for low latency applications and constant delay mode for frame integrity

applications

•

Per-channel A-Law/µ-Law Conversions for both voice and data

128 separate Pseudo-random Bit Sequence (PRBS) test circuits; one per stream. This provides an integrated

Bit Error Rate (BER) test capability to facilitate data path integrity checking

The ZL50073 has two major modes of operation: Connection Mode (normal) and Message Mode. In Connection

Mode, data bytes received at the TDM inputs are switched to timeslots in the output data streams, with mapping

controlled by the Connection Memories. Using Zarlink's Message Mode capability, microprocessor data can be

broadcast to the output data streams on a per-channel basis. This feature is useful for transferring control and

status information to external circuits or other TDM devices.

A non-multiplexed microprocessor port provides access to the internal Data Memory, Connection Memory and

Control Registers used to program ZL50073 options. The port is configurable to interface with either Motorola or

Intel-type microprocessors and is selectable to be either 32 bit or 16 bit.

The mandatory requirements of IEEE 1149.1 standard are supported via the dedicated Test Access Port.

Zarlink Semiconductor Inc.

123 4 5 6 7...67

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与ZL50073GA相关器件

型号	品牌	描述	获取价格	数据表
ZL50073GAC	ZARLINK	32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Str	获取价格
ZL50073GAG2	ZARLINK	32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Str	获取价格
ZL50074	ZARLINK	32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams	获取价格
ZL50074GAC	ZARLINK	32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams	获取价格
ZL50074GAG2	ZARLINK	32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams	获取价格
ZL50074GDC	MICROSEMI	Digital Time Switch, PBGA484, 23 X 23 MM, 1 MM PITCH, PLASTIC, BGA-484	获取价格

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