ZL50060/1
Data Sheet
List of Figures
Figure 1 - ZL50060/1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - ZL50061 PBGA Connections (272 PBGA, 27 mm x 27 mm) Pin Diagram
(as viewed through top of package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3 - ZL50060 PBGA Connections (256 PBGA, 17 mm x 17 mm) Pin Diagram
(as viewed through top of package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4 - 16,384 x 16,384 Channels (16 Mbps), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5 - 8,192 x 8,192 Channels (16 Mbps), Bi-directional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6 - 12,288 by 4,096 Channels Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7 - ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8 - Input and Output Frame Pulse Alignment for Different Data Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 9 - Backplane and Local Input Channel Delay Timing Diagram (assuming 8 Mbps operation) . . . . . . . . . 30
Figure 10 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mbps . . . . . . . . . . . . . . . . 31
Figure 11 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for Data Rate of
8 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 16 Mbps . . . . . . . . . . . 33
Figure 13 - Local/Backplane Port External High Impedance Control Timing (Non-32 Mbps Mode) . . . . . . . . . . . 37
Figure 14 - Local and Backplane Port External High Impedance Control Timing (32Mbps Mode) . . . . . . . . . . . . 41
Figure 15 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch0 Switched to Output Ch0. . . . 43
Figure 16 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch0 Switched to Output Ch13. . . 43
Figure 17 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch13 Switched to Output Ch0. . . 43
Figure 18 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch0 Switched to Output Ch0 . . . . 44
Figure 19 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch0 Switched to Output Ch13 . . . 44
Figure 20 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch13 Switched to Output Ch0 . . . 44
Figure 21 - Examples of BER Transmission Channels on a 16Mbps Output Stream . . . . . . . . . . . . . . . . . . . . . . 45
Figure 22 - Hardware RESET de-assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 23 - Frame Boundary Conditions, ST-BUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 24 - Frame Boundary Conditions, GCI-Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 25 - Input and Output Clock Timing Diagram for ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 26 - Input and Output Clock Timing Diagram for GCI-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 27 - ST-BUS Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps). . . . . . . . . . . . . . . . . . . . 88
Figure 28 - ST-BUS Local/Backplane Data Timing Diagram (32 Mbps, 16 Mbps). . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 29 - GCI-Bus Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps) . . . . . . . . . . . . . . . . . . . 90
Figure 30 - GCI-Bus Local/Backplane Data Timing Diagram (32 Mbps, 16 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 31 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 32 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 33 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 34 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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Zarlink Semiconductor Inc.
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