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ZL50062GAC PDF预览

ZL50062GAC

更新时间: 2024-01-17 18:43:59
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 开关电信转换电路电信电路
页数 文件大小 规格书
68页 887K
描述
16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs

ZL50062GAC 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:BGA, BGA256,16X16,40Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.89
JESD-30 代码:S-PBGA-B256JESD-609代码:e0
长度:17 mm湿度敏感等级:1
功能数量:1端子数量:256
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA256,16X16,40封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):225
电源:1.8,3.3 V认证状态:Not Qualified
座面最大高度:1.8 mm子类别:Other Telecom ICs
标称供电电压:1.8 V表面贴装:YES
电信集成电路类型:DIGITAL TIME SWITCH温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:17 mm
Base Number Matches:1

ZL50062GAC 数据手册

 浏览型号ZL50062GAC的Datasheet PDF文件第2页浏览型号ZL50062GAC的Datasheet PDF文件第3页浏览型号ZL50062GAC的Datasheet PDF文件第4页浏览型号ZL50062GAC的Datasheet PDF文件第5页浏览型号ZL50062GAC的Datasheet PDF文件第6页浏览型号ZL50062GAC的Datasheet PDF文件第7页 
ZL50062/4  
16K-Channel Digital Switch with High Jitter  
Tolerance, Single Rate (2, 4, 8,  
or 16Mbps), and 64 Inputs and 64 Outputs  
Data Sheet  
November 2003  
Features  
Ordering Information  
16,384-channel x 16,384-channel non-blocking  
unidirectional switching.The Backplane and Local  
inputs and outputs can be combined to form a  
non-blocking switching matrix with 64 input  
streams and 64 output streams  
ZL50062GAC 256-Ball PBGA  
ZL50064QCC 256-Pin LQFP  
8,192-channel x 8,192-channel non-blocking  
Backplane input to Local output stream switch  
-40°C to +85°C  
8,192-channel x 8,192-channel non-blocking  
Local input to Backplane output stream switch  
Per-stream bit delay for Local and Backplane  
input streams  
8,192-channel x 8,192-channel non-blocking  
Backplane input to Backplane output switch  
Per-stream advancement for Local and Backplane  
output streams  
8,192-channel x 8,192-channel non-blocking  
Local input to Local output stream switch  
Constant 2-frame throughput delay for frame  
integrity  
Backplane port accepts 32 input and 32 output  
ST-BUS streams with fixed data rates of  
2.048Mbps, 4.096Mbps, 8.192Mbps or  
16.384Mbps  
Per-channel high impedance output control for  
Local and Backplane streams  
Per-channel driven-high output control for Local  
and Backplane streams  
Local port accepts 32 input and 32 output ST-  
BUS streams with fixed data rates of 2.048Mbps,  
4.096Mbps, 8.192Mbps or 16.384Mbps  
Per-channel message mode for Local and  
Backplane output streams  
Exceptional input clock jitter tolerance (17ns)  
Connection memory block programming for fast  
device initialization  
V
V
V
SS (GND)  
DD_IO  
DD_CORE  
RESET  
ODE  
Backplane Data Memories  
(8,192 channels)  
BSTi0-31  
BSTo0-31  
LSTi0-31  
Backplane  
Local  
Backplane  
Interface  
Local  
Interface  
Connection Memory  
(8,192 locations)  
Connection Memory  
(8,192 locations)  
LSTo0-31  
LORS  
Local Data Memories  
BORS  
FP8i  
(8,192 channels)  
FP8o  
FP16o  
C8o  
Input  
Timing Unit  
Output  
Timing  
Unit  
C16o  
Microprocessor Interface  
and Internal Registers  
C8i  
PLL  
Test Port  
V
TMS TDi TDo TCK TRST  
D15-0  
A14-0  
DS CS R/W  
DD_PLL  
DTA  
Figure 1 - ZL50062/4 Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.  

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