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ZL30252LDF1 PDF预览

ZL30252LDF1

更新时间: 2024-02-17 20:15:50
品牌 Logo 应用领域
美高森美 - MICROSEMI 外围集成电路
页数 文件大小 规格书
106页 1651K
描述
Microprocessor Circuit, CMOS, QFN-32

ZL30252LDF1 技术参数

生命周期:Active包装说明:HVQCCN,
Reach Compliance Code:compliantFactory Lead Time:8 weeks
风险等级:5.6其他特性:IT ALSO REQUIRED 3.3V SUPPLY
JESD-30 代码:S-XQCC-N32长度:5 mm
端子数量:32最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE座面最大高度:1 mm
最大供电电压:1.89 V最小供电电压:1.71 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD宽度:5 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

ZL30252LDF1 数据手册

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Register Map: Section 6.2  
ZL30252, ZL30253  
3-Input, 3-Output Any-to-Any Clock  
Multiplier and Jitter Attenuator ICs  
Data Sheet  
January 2018  
Ordering Information  
Features  
ZL30252LDG1  
ZL30252LDF1  
ZL30253LDG1  
ZL30253LDF1  
32 Pin QFN  
32 Pin QFN  
32 Pin QFN  
32 Pin QFN  
Trays  
Tape and Reel  
Trays  
Input Clocks  
Three inputs: two differential/CMOS, one CMOS  
Tape and Reel  
Any input frequency from 1kHz to 1250MHz  
(1kHz to 300MHz for CMOS)  
Matte Tin  
Inputs continually monitored for activity and  
Package size: 5 x 5 mm  
frequency accuracy  
-40 C to +85 C  
Automatic or manual reference switching  
Low-Bandwidth DPLL  
Per-output supply pin with CMOS output  
voltages from 1.5V to 3.3V  
Programmable bandwidth, 14Hz to 500Hz  
Attenuates jitter up to several UI  
Precise output alignment circuitry and per-  
output phase adjustment  
Freerun or digital hold on loss of all inputs  
Digitally controlled phase adjustment  
Per-output enable/disable and glitchless  
start/stop (stop high or low)  
Low-Jitter Fractional-N APLL and 3 Outputs  
Any output frequency from <1Hz to 1035MHz  
General Features  
Automatic self-configuration at power-up from  
external (ZL30252) or internal (ZL30253)  
EEPROM; up to four configs pin-selectable  
High-resolution fractional frequency conversion  
with 0ppm error  
Numerically controlled oscillator mode  
Spread-spectrum modulation mode  
Zero-delay mode with external feedback  
SPI or I2C processor Interface  
Easy-to-configure, encapsulated design  
requires no external VCXO or loop filter  
components  
Each output has independent dividers  
Output jitter is typically 0.16 to 0.28ps RMS  
Easy-to-use evaluation software  
(12kHz-20MHz integration band)  
Applications  
Outputs are CML or 2xCMOS, can interface to  
LVDS, LVPECL, HSTL, SSTL and HCSL  
Frequency conversion, jitter attenuation and  
frequency synthesis in a wide variety of  
equipment types  
In 2xCMOS mode, the P and N pins can be  
different frequencies (e.g. 125MHz and 25MHz)  
IC1P, IC1N  
OC1P, OC1N  
VDDO1  
OC2P, OC2N  
VDDO2  
OC3P, OC3N  
VDDO3  
HSDIV1  
HSDIV1  
HSDIV2  
DIV1  
DIV2  
DIV3  
DPLL  
APLL  
~3.7 to 4.2GHz,  
Fractional-N  
Input Block  
Divider,  
Jitter Filtering,  
Digital Hold  
IC2P, IC2N  
IC3P/GPIO3  
Monitor,  
HSDIV2  
HSDIV3  
Selector  
Figure 10  
Figure 11  
Figure 12  
Microprocessor Port  
(SPI or I2C Serial)  
and HW Control and Status Pins  
XA  
XB  
xtal  
driver  
×2  
Figure 1 - Functional Block Diagram  
1
Microsemi Confidential  
Copyright 2018. Microsemi Corporation. All Rights Reserved.  
 

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