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ZL30254 PDF预览

ZL30254

更新时间: 2023-12-06 20:06:24
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
13页 565K
描述
The ZL30254 is a high-performance, cost efficient, precision clock multiplier optimized for Ethern

ZL30254 数据手册

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ZL30254  
2-In, 2-Out 8kHz/25MHz to 125/156.25MHz  
Clock Multiplier and Jitter Attenuator  
Data Sheet  
April 2016  
Ordering Information  
Features  
ZL30254LDG1  
ZL30254LDF1  
32 Pin QFN  
32 Pin QFN  
Trays  
Tape and Reel  
Input Clocks  
Two CMOS inputs, both 8kHz or 25MHz  
Matte Tin  
Inputs continually monitored for frequency  
Package size: 5 x 5 mm  
accuracy (±1%)  
-40 C to +85 C  
Automatic revertive reference switching  
Low-Bandwidth DPLL  
25Hz bandwidth for jitter attenuation  
±120ppm tracking range  
General Features  
Operates from low-cost 49.152MHz  
Digital hold on loss of all inputs  
fundamental-mode crystal  
Clock Multiplier APLL and Output Clocks  
Status output pins indicate selected input clock,  
holdover, and locked/unlocked states  
Easy-to-configure, encapsulated design  
requires no external VCXO or loop filter  
components  
Input clock selection control pin  
Two CML outputs, both 125MHz or 156.25MHz  
Applications  
Outputs easily interface with CML, LVDS or  
Jitter attenuation, reference selection from dual  
8kHz or 25MHz inputs, frequency multiplication to  
125MHz or 156.25MHz  
LVPECL components  
Output jitter <1ps RMS (12kHz-20MHz)  
OC1P, OC1N  
VDDO1  
DPLL  
Jitter Filtering,  
Digital Hold  
APLL  
Low-Jitter VCO  
Input Block  
Divider,  
IC1  
IC2  
DIV  
Monitor,  
Selector  
OC2P, OC2N  
VDDO2  
XA  
XB  
HW Control and Status Pins  
xtal  
×2  
driver  
Figure 1 - Functional Block Diagram  
1
Microsemi Confidential  
Copyright 2016. Microsemi Corporation. All Rights Reserved.  
 

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