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Z9309CT

更新时间： 2024-02-01 21:54:41
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 70K
描述
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO16, TSSOP-16

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中文翻译

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Z9309CT 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP-16
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.85
输入调节：STANDARDJESD-30 代码：R-PDSO-G16
JESD-609代码：e0长度：5 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.008 A
功能数量：1反相输出次数：
端子数量：16实输出次数：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.25 ns座面最大高度：1.2 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

Z9309CT 数据手册

 浏览型号Z9309CT的Datasheet PDF文件第1页浏览型号Z9309CT的Datasheet PDF文件第3页浏览型号Z9309CT的Datasheet PDF文件第4页浏览型号Z9309CT的Datasheet PDF文件第5页浏览型号Z9309CT的Datasheet PDF文件第6页浏览型号Z9309CT的Datasheet PDF文件第7页 
Z9305/Z9309  
Multiple Z9305 and Z9309 devices can accept the same input  
clock and distribute it. In this case, the skew between the  
outputs of two devices is guaranteed to be less than 700 ps.  
Product Description  
The Z9309 is a low cost 3.3V zero delay buffer designed to  
distribute high speed clocks in PC system devices and  
SDRAM modules and is available in a 16-pin SOIC or TSSOP  
package. The Z9305 is an 8-pin version of the Z9309 and it  
accepts one reference input and drives out five low skew  
clocks. The devices have an on-chip PLL which locks to an  
input clock on the REF pin. The PLL feedback is on-chip and  
is obtained from the CLKOUT pad.  
All outputs have less than 200 ps of cycle-cycle jitter. The input  
to output propagation delay is guaranteed to be less than 350  
ps, and the output to output skew is guaranteed to be less than  
250 ps.  
Connection Diagram  
The Z9309 has two banks of four outputs each, which can be  
controlled by the Select inputs as shown in the Table 1. If all  
output clocks are not required, Bank B can be tri-stated. The  
select inputs also allow the input clock to be directly applied to  
the output for chip and system testing purposes.  
REF  
LKA1  
LKA2  
VDD  
GND  
LKB1  
LKB2  
S2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CLKOUT  
CLKA4  
CLKA3  
VDD  
REF  
CLK2  
CLK1  
GND  
1
2
3
4
8
7
6
5
CLKOU  
CLK4  
VDD  
GND  
The Z9305 and Z9309 PLLs enter a Power Down mode when  
there are no rising edges on the REF input. In this state, the  
outputs are tri-stated and the PLL is turned off, resulting in less  
than 50 uA of current draw. The Z9309 PLL shuts down in one  
additional case as shown in Table 1.  
CLK3  
CLKB4  
CLKB3  
S1  
Pin Description (Z9305)  
PIN No.  
Pin Name  
REF[1]  
I/O  
I
Description  
1
2
3
4
5
6
7
8
Input reference frequency, 5.0 V tolerant input  
Buffered clock output  
CLK2[1]  
CLK1[1]  
GND  
O
O
I
Buffered clock output  
Ground  
CLK3[1]  
O
Buffered clock output  
VDD  
3.3V supply  
CLK4[1]  
CLKOUT[1]  
O
O
Buffered clock output  
Buffered clock output, internal feedback on this pin  
Pin Description (9309)  
PIN No.  
Pin Name  
REF[1]  
CLKA1[1]  
CLKA2[1]  
VDD  
I/O  
I
Description  
Input reference frequency, 5.0 V tolerant input  
Clock output, bank A  
Clock output, bank A  
3.3V supply  
1
2
O
O
I
3
4
5
GND  
I
Ground  
6
CLKB1[1]  
CLKB2[1]  
S2[2]  
O
O
I
Clock output, bank B  
Clock output, bank B  
Select input pin, bit 2  
Select input pin, bit 1  
Clock output, bank B  
Clock output, bank B  
Ground  
7
8
9
S1[2]  
I
10  
11  
12  
13  
14  
15  
16  
CLKB3[1]  
CLKB4[1]  
GND  
O
O
VDD  
3.3V supply  
CLKA3[1]  
CLKA4[1]  
CLKOUT[1]  
O
O
Clock output, bank A  
Clock output, bank A  
O
Buffered output, internal feedback on this pin.  
Notes:  
1. Includes weak pull-down.  
2. Includes weak pull-up.  
Document #: 38-07196 Rev. **  
Page 2 of 7  
 
 
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