Datasheet > Z9308-2CT

Z9308-2CT

更新时间： 2024-01-06 05:11:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
10页	84K
描述
PLL Based Clock Driver, PDSO16, TSSOP-16

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技术参数
数据手册

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Z9308-2CT 技术参数

生命周期：	Transferred	零件包装代码：	TSSOP
包装说明：	,	针数：	16
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.6	JESD-30 代码：	R-PDSO-G16
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	端子数量：	16
封装主体材料：	PLASTIC/EPOXY	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	认证状态：	Not Qualified
表面贴装：	YES	端子形式：	GULL WING
端子位置：	DUAL	Base Number Matches：	1

Z9308-2CT 数据手册

Z9308

Zero Delay Clock Buffer

Preliminary

AAC Electrical Characteristics

Parameter

Symbol Min Typ Max

Units

Conditions

30 pF load (all devices)

Output Frequency (Z9308)

Duty Cycle (T₂/T₁) ⁽¹⁾

Output Rise Time⁽¹⁾

t₁

150

MHz

Measured @ 1.4V (-1,-2,-3,-4 devices)

t₃

2.5

nSec

Measured between 0.8V & 2.0V, 30 pF

Load (-1,-2,-3,-4 devices)

Output Rise Time⁽¹⁾

Output Fall Time⁽¹⁾

Output to Output Skew

t₃

t₄

1.5

2.5

1.5

nSec

Measured between 0.8V & 2.0V, 20 pF

Load (-1,-2,-3,-4 devices)

Measured between 0.8V & 2.0V, 30 pF

Load (-1,-2,-3,-4 devices)

Measured between 0.8V & 2.0V, 20 pF

Load (-1,-2,-3,-4 devices)

t₅

t₆

250

pSec

All output equally loaded @ 66MHz

Delay, REF Rising Edge to

+ 350

Measured at V_DD/2

All outputs equally loaded.

FBK Rising Edge⁽¹⁾

Device to Device Skew⁽¹⁾

Cycle to Cycle Jitter⁽¹⁾

(-1,-4 devices)

t₇

700

200

pSec

Measured at V_DD/2 on FBK pins of devices

Measured at 66.67 MHz, loaded outputs

Cycle to Cycle Jitter⁽¹⁾

(-2,-3 devices)

Maximum PLL Lock Time⁽¹⁾

500

1.0

pSec

Measured at 66.67 MHz, loaded outputs

tLOCK

Stable power supply, valid clocks

presented on REF and FBK pins

Notes:

1. Parameter is guaranteed by design and characterization. Not 100% tested in production. All parameters specified

with equally loaded outputs, input rise/fall max 2nS.

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571

Rev.1.3

3/9/00

Page 4 of 10

1 2 345 6 7...10

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