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Z9308-2CT PDF预览

Z9308-2CT

更新时间: 2024-02-29 18:40:33
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
10页 84K
描述
PLL Based Clock Driver, PDSO16, TSSOP-16

Z9308-2CT 技术参数

生命周期:Transferred零件包装代码:TSSOP
包装说明:,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.6JESD-30 代码:R-PDSO-G16
逻辑集成电路类型:PLL BASED CLOCK DRIVER端子数量:16
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
表面贴装:YES端子形式:GULL WING
端子位置:DUALBase Number Matches:1

Z9308-2CT 数据手册

 浏览型号Z9308-2CT的Datasheet PDF文件第1页浏览型号Z9308-2CT的Datasheet PDF文件第3页浏览型号Z9308-2CT的Datasheet PDF文件第4页浏览型号Z9308-2CT的Datasheet PDF文件第5页浏览型号Z9308-2CT的Datasheet PDF文件第6页浏览型号Z9308-2CT的Datasheet PDF文件第7页 
Z9308  
Zero Delay Clock Buffer  
Preliminary  
Z9308 Configurations  
Device  
Feedback From  
Bank A or Bank B  
Bank A  
Bank A Frequency  
Bank B Frequency  
Reference  
Reference/2  
Reference  
Reference  
2X Ref.  
Z9308-1  
Z9308-2  
Reference  
Reference  
2X Ref.  
Bank B  
Z9308-3  
Z9308-4  
Bank A  
2X Ref.  
Bank B  
4X Ref.  
Bank A or Bank B  
2X Ref.  
2X Ref.  
Pin Description  
PIN No.  
Pin Name  
REF(1)  
CLKA1  
CLKA2  
VDD  
I/O  
I
Description  
1
2
Input reference frequency, 5.0 V tolerant input.  
Clock Output, Bank A.  
Clock Output, Bank A.  
3.3 V Supply  
O
O
I
3
4
5
GND  
I
Ground  
6
CLKB1  
CLKB2  
S2  
O
O
I
Clock Output, Bank B.  
Clock Output, Bank B.  
Select Input pin, bit 2.  
Select Input pin, bit 1  
Clock Output, Bank B.  
Clock Output, Bank B.  
Ground  
7
8
9
S1  
I
10  
11  
12  
13  
14  
15  
16  
CLKB3  
CLKB4  
GND  
O
O
VDD  
3.3V supply  
CLKA3  
CLKA4  
FBK  
O
O
I
Clock Output, Bank A.  
Clock Output, Bank A.  
PLL feedback input.  
Note 1: Includes internal week pull-downs.  
Maximum Ratings  
This device contains circuitry to protect the inputs  
against damage due to high static voltages or electric  
field; however, precautions should be taken to avoid  
application of any voltage higher than the maximum  
rated voltages to this circuit. For proper operation, Vin  
and Vout should be constrained to the range:  
VSS<(Vin or Vout)<VDD  
Unused inputs must always be tied to an appropriate  
logic voltage level (either VSS or VDD).  
Voltage Relative to VSS:  
Voltage Relative to VDD:  
-0.5V  
0.5V  
-65oC to + 150oC  
0oC to +85oC  
7V  
Storage Temperature:  
Operating Temperature:  
Maximum Power Supply:  
Reference Input Voltage:  
-.5 to 7V  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571  
Rev.1.3  
3/9/00  
Page 2 of 10  

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