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Z86E733 PDF预览

Z86E733

更新时间: 2024-11-25 01:21:11
品牌 Logo 应用领域
ZILOG /
页数 文件大小 规格书
10页 33K
描述
PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION

Z86E733 数据手册

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PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION  
1
Z86E33/733/E34  
Z86E43/743/E44  
1
®
CMOS Z8 OTP MICROCONTROLLERS  
FEATURES  
Programmable Crystal Oscillator, EPROM Protect,  
RAM Protect, Auto Latch Disable, Permanent WDT,  
32 KHz Oscillator, and EPROM /Test Mode Disable  
ROM  
(KBytes)  
RAM*  
(Bytes)  
I/O  
Lines  
Speed  
(MHz)  
Device  
Z86E33  
Z86733  
Z86E34  
Z86E43  
Z86743  
Z86E44  
4
8
237  
237  
237  
236  
236  
236  
24  
24  
24  
32  
32  
32  
16  
16  
16  
16  
16  
16  
Fast Instruction Pointer: 0.6µs  
16  
4
Two Standby Modes: STOP and HALT  
24/32 Input and Output Lines  
8
16  
Digital Inputs CMOS Levels, Schmitt-Triggered  
Software Programmable Low EMI Mode  
Note: *General-Purpose  
Standard Temperature (V = 3.5V to 5.5V)  
CC  
Two Programmable 8-Bit Counter/Timers Each with a 6-  
Extended Temperature (V = 4.5V to 5.5V)  
CC  
Bit Programmable Prescaler  
28-Pin DIP/SOIC/PLCC Packages (E33/733/E34)  
40-Pin DIP Package (E43/743/E44)  
Six Vectored, Priority Interrupts from Six Different  
Sources  
44-Pin PLCC/QFP Packages (E43/743/E44)  
Auto Latches  
Software Enabled Watch-Dog Timer (WDT)  
Auto Power-On Reset (POR)  
Two Comparators  
Push-Pull/Open-Drain Programmable on  
Port 0, Port 1, and Port 2  
Low-Power Consumption: 60 mW  
On-Chip Oscillator that Accepts a Crystal, Ceramic  
Resonator, LC, RC, or External Clock Drive  
GENERAL DESCRIPTION  
The Z86E33/733/E34/E43/743/E44 8-bit CMOS One-Time  
Programmable (OTP) microcontrollers are members of  
Zilog's Z8 single-chip microcontroller family featuring en-  
hanced wake-up circuitry, programmable Watch-Dog Tim-  
ers, Low Noise EMI options, and easy hardware/software  
system expansion capability.  
For applications demanding powerful I/O capabilities, the  
Z86E33/733/E34 have 24 pins and the Z86E43/743/E44  
have 32 pins of dedicated input and output. These lines are  
grouped into four ports, eight lines per port, and are config-  
urable under software control to provide timing, status sig-  
nals, and parallel I/O with or without handshake, and ad-  
dress/data bus for interfacing external memory.  
®
Four basic address spaces support a wide range of mem-  
ory configurations. The designer has easy access to regis-  
ter mapped peripheral and I/O circuits.  
Notes: All Signals with a preceding front slash, "/", are  
active Low, e.g., B//W (WORD is active Low); /B/W (BYTE  
is active Low, only).  
CP97DZ83300  
P R E L I M I N A R Y  
1

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