Datasheet > XRT72L71IQ160

XRT72L71IQ160

更新时间： 2025-07-21 15:58:31

品牌	Logo	应用领域
艾科嘉 - EXAR		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
104页	539K
描述
ATM Network Interface, 1-Func, CMOS, PQFP160, 28 X 28 MM, PLASTIC, QFP-160

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XRT72L71IQ160 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFP, QFP160,1.2SQ	针数：	160
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.9	Is Samacsys：	N
应用程序：	ATM	JESD-30 代码：	S-PQFP-G160
JESD-609代码：	e0	长度：	28 mm
功能数量：	1	端子数量：	160
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP160,1.2SQ	封装形状：	SQUARE
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	4.07 mm	子类别：	ATM/SONET/SDH ICs
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	ATM/SONET/SDH NETWORK INTERFACE
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	28 mm	Base Number Matches：	1

XRT72L71IQ160 数据手册

XRT72L71

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DS3 ATM UNI/CLEAR CHANNEL FRAMER

REV. P1.0.5

PRELIMINARY

• Detects and generates interrupts upon “Detection

of HEC Byte errors”, “Change in LCD (Loss of Cell

Delineation) condition” and “Receipt of OAM Cell”.

• The size of the “TxFIFO” is 16 cells. However, the

operating depth can be configured to be 4, 8, 12 or

16 cells.

The Receive UTOPIA Interface Block

• Supports write operations (from the ATM Layer

device) at rates upto 50MHz.

• Provides a “UTOPIA Level -2” compliant interface to

• Detects and generates interrupts upon “Detection

of Parity Errors”, “Detection of RUNT cells” and

“Overrun of TxFIFO”.

either the ATM or the ATM Adaptation Layer.

• Can be configured to operate in either the “Single-

PHY” or “Multi-PHY” Modes.

Transmit Cell Processor Block

• Supports either “Cell-Level” or “Octet-Level” Hand-

shaking.

• The Transmit Cell Processor will read in ATM cells

from the Transmit FIFO (if available) for further

processing.

• Receive UTOPIA Data Bus can be configured to be

either 8 or 16-bits wide.

• If no cell is available within the Transmit FIFO, then

the Transmit Cell Processor will automatically gen-

erate an Idle cell. The UNI is equipped with on-chip

registers to allow for the generation of customized

Idle cells.

• The RxFIFO, within the Receive UTOPIA Interface

block will temporarily hold any ATM cells that pass

through the Receive Cell Processor, where they can

be read out by the ATM Layer processor, over the

Receive UTOPIA Data Bus.

• The UNI provides 54 bytes of on-chip RAM that

allows for the generation and transmission of “user-

specified” OAM cells. The Transmit Cell Processor

will generate and transmit these OAM cells upon

software command.

• The size of the “RxFIFO” is 16 cells.

• Supports read operations (from the ATM Layer

device) at rates upto 50MHz.

• Detects and generates interrupts upon “Detection

of RUNT cells” and “Overrun of RxFIFO”.

• The Transmit Cell Processor block will also com-

pute and insert a CRC-10 value into each “out-

bound” OAM cell, per ITU-T I.610.

THE TRANSMIT SECTION

The purpose of the Transmit section of the XRT72L71

DS3 ATM UNI is to allow a local ATM Layer (or ATM

Adaptation Layer) processor to transmit ATM Cell da-

ta to a remote piece of equipment via a public or

leased DS3 transport medium.

• The Transmit Cell Processor will (optionally) scramble

the Cell Payload bytes and (optionally) compute

and insert the HEC (Header Error Check) byte. This

HEC byte will be inserted into the fifth octet of each

cell prior to being transferred to the Transmit PLCP

Processor (or the Transmit DS3 Framer).

The Transmit Section of the XRT72L71 DS3 UNI con-

sists of the following functional blocks.

Transmit PLCP Processor Block

• Transmit UTOPIA Interface Block

• Transmit Cell Processor Block

• Transmit PLCP Processor Block

• Transmit DS3 Framer Block

• The Transmit PLCP Processor will pack 12 ATM cells

into each PLCP frame and automatically determine

the nibble-stuffing option of the current PLCP frame.

These PLCP frames will also include an overhead

byte that reflect BIP-8 (Bit Interleaved Parity) calcula-

tion results, a byte that reflects the current stuffing

option status of the current PLCP frame, Path Over-

head and Identifier bytes, and diagnostic-related

bytes reflecting any detected BIP-8 errors and

alarm conditions detected in the Receive section of

the UNI chip.

Each of these functional blocks, within the Transmit

Section (of the UNI/Framer) will do the following:

Transmit UTOPIA Interface Block

• Can be configured to operate in either the “Single-

PHY” or Multi-PHY” Mode.

Transmit DS3 Framer Block

• Supports either the “Cell-Level” or “Octet-Level”

Handshaking Mode.

• These PLCP frames (or “Direct Mapped” ATM cells)

will be inserted into the payload of an outgoing DS3

frame, for transmission to the “Remote” Terminal, by

the Transmit DS3 Framer.

• Transmit UTOPIA Data Bus can be configured to be

either 8 or 16-bits wide.

• Allow the ATM Layer processor to write ATM cells

into the Transmit FIFO (within the Transmit UTOPIA

Interface block) via a standard UTOPIA Level 2

interface.

• The Transmit DS3 Framer will transmit FEAC (Far

End Alarm & Control) messages to the Remote Ter-

minal Equipment via an on-chip FEAC Transceiver.

1 2 345 6 7...104

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