Datasheet > XRT72L71IQ160

XRT72L71IQ160

更新时间： 2025-07-21 15:58:31

品牌	Logo	应用领域
艾科嘉 - EXAR		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
104页	539K
描述
ATM Network Interface, 1-Func, CMOS, PQFP160, 28 X 28 MM, PLASTIC, QFP-160

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

XRT72L71IQ160 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFP, QFP160,1.2SQ	针数：	160
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.9	Is Samacsys：	N
应用程序：	ATM	JESD-30 代码：	S-PQFP-G160
JESD-609代码：	e0	长度：	28 mm
功能数量：	1	端子数量：	160
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP160,1.2SQ	封装形状：	SQUARE
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	4.07 mm	子类别：	ATM/SONET/SDH ICs
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	ATM/SONET/SDH NETWORK INTERFACE
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	28 mm	Base Number Matches：	1

XRT72L71IQ160 数据手册

áç

PRELIMINARY

XRT72L71

DS3 ATM UNI/CLEAR CHANNEL FRAMER

REV. P1.0.5

the DS3 Framing/Overhead Bits. This procedure

will result in either extracting PLCP frame data or

“Direct-Mapped” ATM Cell data, from the payload

portion of the incoming DS3 data stream.

SYSTEM/FUNCTIONAL DESCRIPTION

FUNCTIONAL DESCRIPTION

The XRT72L71 DS3 ATM UNI/Framer IC can be con-

figured to operate in either the “ATM UNI” or in the

“Clear-Channel-Framer” Mode.

• The Receive DS3 Framer can be used to receive

FEAC (Far End Alarm & Control) messages via an

on-chip FEAC Transceiver.

A brief listing of the features and description for each

of these operating modes is presented below.

• The Receive DS3 Framer includes an on-chip

LAPD Receiver along with 88 bytes of on-chip RAM

that can receive incoming path maintenance data

link messages from the Remote Terminal Equip-

ment.

THE ATM UNI MODE OF OPERATION

When the XRT72L71 UNI/Framer has been config-

ured to operate in the “ATM UNI” Mode, it can func-

tionally be subdivided into 6 different sections, as

shown in Figure 2.

• Detects and generates interrupts upon “Detection

of P and CP-bit Errors”, “Change of State in LOS,

AIS, OOF and FERF”, “Receipt of New LAPD

(PMDL) Message”, “Validation and Removal of

FEAC Message”.

• Receive Section

• Transmit Section

• Microprocessor Interface Section

• Performance Monitor Section

• Test and Diagnostic Section

• Line Interface Unit Scan Drive Section

NOTE: The Receive DS3 Framer supports both M13 and C-

bit Parity Frame Formats.

The Rx PLCP Processor Block

The features of each of these functional sections are

briefly outlined below.

• The Receive PLCP Processor will identify the frame

boundary of each incoming PLCP frame, extract

and process the overhead bytes of these PLCP

frames (applies only if the UNI is operating in the

PLCP Mode). The Receive PLCP Processor will

also perform some error checking on the incoming

PLCP frames. The Receive PLCP Processor will

inform the Remote Terminal Equipment of the

results of this error-checking by internally routing

these results to the “Near-End” Transmit PLCP Pro-

cessor, for transmission back out to the RemoteTer-

minal Equipment.

THE RECEIVE SECTION

The purpose of the Receive Section of the XRT72L71

DS3 ATM UNI is to allow a local ATM Layer (or ATM

Adaptation Layer) processor to receive ATM cell data

from a remote piece of equipment via a public or

leased DS3 transport medium.

The Receive Section of the XRT72L71 DS3 UNI con-

sists of the following functional blocks.

• Receive DS3 Framer Block

The Rx Cell Processor Block

• Receive PLCP (Physical Layer Convergence Proto-

col) Processor Block

• The Receive Cell Processor will perform the follow-

ing functions:

• Receive Cell Processor Block

– Cell Delineation

• Receive UTOPIA Interface Block

– HEC Byte Verification of incoming cells

(optional)

Each of these functional blocks, within the Receive

Section of the UNI Framer will do the following:

– Cell-payload de-scrambling (optional)

– Idle cell detection and removal (optional)

– User and OAM Cell Filtering (optional)

– OAM Cell Processing (optional)

The Rx DS3 Framer Block

• Capable of receiving data, from the LIU IC, in either

the “Single-Rail” or “Dual-Rail” mode.

• The UNI provides 108 bytes of on-chip RAM that

allows for the reception and processing of selected

OAM cells.

• Capable of “sampling” the “inbound” DS3 data (at

the “RxPOS” and “RxNEG” input pins) upon either

the rising or falling edge of the “RxLineClk” signal.

• The Receive Cell Processor block will also verify

the CRC-10 value within all received OAM cells, per

ITU-T I.610.

• The Receive DS3 Framer will synchronize to the

incoming DS3 data stream and remove or process

1 234 5 6 7...104

中文翻译

下载PDF

与XRT72L71IQ160相关器件

型号	品牌	获取价格	描述	数据表
XRT72L73IB	ETC	获取价格	Telecommunication IC
XRT72L74IB	ETC	获取价格	Telecommunication IC
XRT72L74IQ160	EXAR	获取价格	ATM Network Interface, 1-Func, CMOS, PBGA352, 35 X 35 MM, PLASTIC, BGA-352
XRT7300	EXAR	获取价格	E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7300	PULSE	获取价格	T3/DS3/E3/STS-1 TRANSFORMERS
XRT7300IV	EXAR	获取价格	E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302	PULSE	获取价格	T3/DS3/E3/STS-1 TRANSFORMERS
XRT7302IQ80	EXAR	获取价格	PCM Transceiver, 2-Func, E-3, BICMOS, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-80
XRT7302IV	ETC	获取价格	PCM Transceiver
XRT73L00	EXAR	获取价格	E3/DS3/STS-1 LINE INTERFACE UNIT

产品中心

服务支持

精选活动

关于我们

帮助中心

XRT72L71IQ160

XRT72L71IQ160 技术参数

XRT72L71IQ160 数据手册

与XRT72L71IQ160相关器件

与XRT72L71IQ160相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

XRT72L71IQ160

XRT72L71IQ160 技术参数

XRT72L71IQ160 数据手册

与XRT72L71IQ160相关器件

与XRT72L71IQ160相关文章

您还可以找

您在本页遇到什么问题？