Datasheet > XRT7295AEIWTR-F

XRT7295AEIWTR-F

更新时间： 2022-09-29 19:40:44

品牌	Logo	应用领域
艾科嘉 - EXAR		/
页数	文件大小	规格书
15页	964K
描述
IC E3 LINE RECEIVER 20SOJ

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XRT7295AEIWTR-F 数据手册

XRT7295AE

PINDESCRIPTION

Pin #

Symbol

Type

Description

GNDA

R_IN

AnalogGround.

Receive Input. Unbalanced analog receive input

3,6

TMC1-TMC2

Test Mode Control 1 and 2. Internal test modes are enabled within the device

by using TMC1 and TMC2. Users must tie these pins to the ground plane.

4,5

LPF-1-LPF-2

RLOS

PLL Filter 1 and 2. An external capacitor (0.1µF +/-20%) is connected

between these pins (See Figure 3).

Receive Loss-of-Signal. This pin is set high on loss of signal at the receive

input.

RLOL

Receive PLL Loss-of-Lock. This pin is set high on loss of PLL frequency lock.

GNDD

Digital Ground for PLL Lock. Ground lead for all circuitry running

synchronously with PLL clock.

GNDC

V_DDD

Digital Ground for EXCLK. Ground lead for all circuitry running

synchronously with EXCLK.

5V Digital Supply (+/-10%) for PLL Clock. Power for all circuitry running

synchronously with PLL clock.

V_DDC

5V Digital Supply (+/-10%) for EXCLK. Power for all circuitry running

synchronously with EXCLK.

EXCLK

External Reference Clock. A valid E3 (34.368MHz +/-100ppm) clock must be

provided at this input. The duty cycle of EXCLK, referenced to V_DD/2 levels,

must be 40%-60%.

RCLK

Receive Clock. Recovered clock signal to the terminal equipment.

RNDATA

Receive Negative Data. Negative pulse data output to the terminal

equipment.

RPDATA

ICT

Receive Positive Data. Positive pulse data output to the terminal equipment.

Output In-Circuit Test Control (Active-Low). If ICT is forced low, all digital

output pins (RCLK, RPDATA, RNDATA, RLOS, RLOL) are placed in a high-

impedance state to allow for in-circuit testing.

REQB

Receive Equalization Bypass. A high on this pin bypasses the internal

equalizer. A low places the equalizer in the data path.

LOSTHR

Loss-of-Signal Threshold Control. The voltage forced on this pin controls the

input loss-of-signal threshold. Three settings are provided by forcing the GND,

V_DD/2, or V_DDat LOSTHR.

V_DDA

5V Analog Supply (+/-10%).

Rev. 2.0.0

1 234 5 6 7...15

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