Datasheet > XPS628303ADRLR

XPS628303ADRLR

更新时间： 2023-09-03 20:32:56

品牌	Logo	应用领域
德州仪器 - TI		转换器
页数	文件大小	规格书
37页	3350K
描述
采用小型 QFN 和 SOT583 封装、精度为 1% 的 2.25V 至 5.5V、3A 降压转换器 \| DRL \| 8 \| -40 to 125

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XPS628303ADRLR 数据手册

TPS628303

ZHCSNO6 –FEBRUARY 2023

www.ti.com.cn

5 Device Options

PART NUMBER

TPS628303ARZER⁽¹⁾

TPS628303ADRLR⁽¹⁾

OUTPUT CURRENT

OCP MODE

PACKAGE

OUTPUT VOLTAGE

WQFN-HR

Hiccup

3 A

Adjustable

SOT583

OCP/OVP

Latch-off

TPS628303BDRLR⁽¹⁾

(1) Preview status

6 Pin Configuration and Functions

VIN

GND

MODE

VIN

GND

MODE

VOS

图6-2. DRL Package 8-Pin SOT Top View

图6-1. RZE Package 8-Pin WQFN Top View

表6-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

VIN

PWR

Input voltage pin. Connect the input capacitor as close as possible between V_INand GND.

Device enable pin. To enable the device, this pin must be pulled high. Pulling this pin low

disables the device. Do not leave this pin unconnected.

GND

Ground pin.

PWR

Switch pin of the power stage

The device runs in PSM/PWM mode when this pin is pulled low and in forced-PWM mode

when pulled high. This event can also be done when the device is in-operation. Do not leave

this pin floating.

MODE

Power good open-drain output pin. The pullup resistor can be connected to voltages up to

5.5 V. If unused, leave this pin floating.

Feedback pin. Connect the resistive output voltage divider to this pin.

VOS

Output voltage sense pin. This pin must be connected directly after the inductor.

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