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XO52CTFL6050M PDF预览

XO52CTFL6050M

更新时间: 2024-12-02 03:28:15
品牌 Logo 应用领域
威世 - VISHAY 输出元件石英晶振
页数 文件大小 规格书
3页 75K
描述
XO, Clock, CRYSTAL OSCILLATOR, CLOCK, 50 MHz, HCMOS/TTL OUTPUT, HALOGEN FREE AND ROHS COMPLIANT, RESISTANCE WELD, METAL PACKAGE-8/4

XO52CTFL6050M 数据手册

 浏览型号XO52CTFL6050M的Datasheet PDF文件第2页浏览型号XO52CTFL6050M的Datasheet PDF文件第3页 
XO-52  
Vishay Dale  
Half Size Clock Oscillator Enable/Disable  
FEATURES  
• Size: 8 pin half size  
• Industry standard  
• Tri-state enable/disable  
• Wide frequency range  
• Low cost  
• Resistance weld package  
• 5 V  
• Compliant to RoHS Directive 2002/95/EC  
The XO-52 series oscillator is half size, has tri-state  
enable/disable controlled function. The metal package with  
pin 4 case ground acts as shielding to minimize EMI  
radiation.  
• Halogen-free according to IEC 61249-2-21 definition  
STANDARD ELECTRICAL SPECIFICATIONS  
PARAMETER  
SYMBOL  
CONDITION  
VALUE  
1.000 MHz to 100.000 MHz  
25 ppm, 50 ppm, 100 ppm  
0 ºC to 70 ºC  
Frequency range  
Frequency stability (1)  
FO  
-
all conditions  
Operating temperature range  
TOPR  
-
- 40 ºC to + 85 ºC (option)  
- 55 ºC to + 125 ºC  
5.0 V 10 ꢀ  
Storage temperature range  
Power supply voltage  
Aging (first year)  
TSTG  
VDD  
-
-
25 ºC 3 ºC  
5 ppm  
1.000 MHz to 23.999 MHz  
20 mA max.  
24.000 MHz to 49.999 MHz  
30 mA max.  
Supply current  
IDD  
50.000 MHz to 69.999 MHz  
40 mA max.  
70.000 MHz to 100.000 MHz  
60 mA max.  
Output symmetry  
Rise time  
Sym  
tr  
at 1/2 VDD  
40 ꢀ/60 ꢀ (45 ꢀ/55 ꢀ option)  
10 ns max.  
20 ꢀ VDD to 80 ꢀ VDD  
Fall time  
tf  
80 ꢀ VDD to 20 ꢀ VDD  
10 ns max.  
VOH  
VOL  
-
-
-
-
-
-
-
90 ꢀ VDD min.  
Output voltage  
Output load  
10 ꢀ VDD max.  
TTL load  
1 TTL to 10 TTL  
to 50M: 50 pF  
HCMOS load  
ts  
to 70M: 30 pF  
to 100M: 15 pF  
Start-up time  
10 ms max.  
pin 1 = H or open (output active at pin 5)  
pin 1 = L (high impedance at pin 5)  
Pin 1, tri-state function  
-
Note  
(1)  
Include: 25 °C tolerance, operating temperature range, input voltage change, aging, load change, shock vibration  
DIMENSIONS in inches [millimeters]  
HCMOS TEST CIRCUIT  
A
#1  
#4  
Test Point  
CMOS Load  
CL (1)  
CL = 15 pF or 50 pF  
(see individual  
spec. sheet)  
MARKING  
AREA  
#8  
#1  
#5  
#4  
+ 5.0 V  
+ 3.3 V  
0.508  
[12.9] max.  
0.01 µF  
V
0.300 0.005  
[7.62 0.13]  
#8  
#5  
0.300 0.005  
[7.62 0.13]  
Note  
INH  
(1) Includes Stray and Probe Capacitance Enable/Disable function  
0.580 [12.9] max.  
0.031 0.003  
[0.8 0.1]  
HCMOS OUTPUT WAVEFORM  
0.220  
Tr  
Tf  
[5.6] max.  
VOH  
90 % VDD  
50 % VDD  
ENABLE/DISABLE FUNCTION  
INPUT (PIN 1) OUTPUT (PIN 5)  
PIN CONNECTION  
#1 N.C.  
#4 GND  
VOL  
0.268  
[6.80] max.  
10 % VDD  
GND  
OPEN  
VIH 2.2 VDC  
ENABLE  
ENABLE  
0.018 0.003  
[0.45 0.1]  
#5 OUTPUT  
T1  
#8  
VDD  
T1  
T0  
SYMMETRY =  
x 100 %  
T0 = 1/Fo  
Document Number: 35025  
Revision: 08-Mar-11  
For technical questions, contact: frequency@vishay.com  
www.vishay.com  
27  

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