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XCS30XL-3BG256C

更新时间： 2024-11-17 23:00:03
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赛灵思 - XILINX 现场可编程门阵列栅
页数 文件大小 规格书
82页 848K
描述
Spartan and Spartan-XL Families Field Programmable Gate Arrays

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XCS30XL-3BG256C 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：PLASTIC, BGA-256
针数：256Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.84
JESD-30 代码：S-PBGA-B256JESD-609代码：e0
长度：27 mm湿度敏感等级：3
可配置逻辑块数量：576等效关口数量：10000
输入次数：196逻辑单元数量：576
输出次数：196端子数量：256
最高工作温度：85 °C最低工作温度：
组织：576 CLBS, 10000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA256,20X20,50
封装形状：SQUARE封装形式：GRID ARRAY
电源：3.3 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：2.55 mm
子类别：Field Programmable Gate Arrays最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：Tin/Lead (Sn63Pb37)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM宽度：27 mm
Base Number Matches：1

XCS30XL-3BG256C 数据手册

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Spartan and Spartan-XL Families  
Field Programmable Gate Arrays  
0
0
DS060 (v1.6) September 19, 2001  
Product Specification  
•
System level features  
Introduction  
-
-
-
-
Available in both 5V and 3.3V versions  
On-chip SelectRAM™ memory  
Fully PCI compliant  
Full readback capability for program verification  
and internal node observability  
™
The Spartan and the Spartan-XL families are a high-vol-  
ume production FPGA solution that delivers all the key  
requirements for ASIC replacement up to 40,000 gates.  
These requirements include high performance, on-chip  
RAM, core solutions and prices that, in high volume,  
approach and in many cases are equivalent to mask pro-  
grammed ASIC devices.  
-
-
-
-
-
-
Dedicated high-speed carry logic  
Internal 3-state bus capability  
Eight global low-skew clock or signal networks  
IEEE 1149.1-compatible Boundary Scan logic  
Low cost plastic packages available in all densities  
Footprint compatibility in common packages  
The Spartan series is the result of more than 14 years of  
FPGA design experience and feedback from thousands of  
customers. By streamlining the Spartan series feature set,  
leveraging advanced process technologies and focusing on  
total cost management, the Spartan series delivers the key  
features required by ASIC and other high-volume logic  
users while avoiding the initial cost, long development  
cycles and inherent risk of conventional ASICs. The Spar-  
tan and Spartan-XL families in the Spartan series have ten  
members, as shown in Table 1.  
•
Fully supported by powerful Xilinx development system  
-
-
-
Foundation Series: Integrated, shrink-wrap  
software  
Alliance Series: Dozens of PC and workstation  
third party development systems supported  
Fully automatic mapping, placement and routing  
Additional Spartan-XL Features  
Spartan and Spartan-XL Features  
•
•
•
•
•
•
•
•
•
•
•
•
•
3.3V supply for low power with 5V tolerant I/Os  
Power down input  
Note: The Spartan series devices described in this data  
sheet include the 5V Spartan family and the 3.3V  
Spartan-XL family. See the separate data sheet for the 2.5V  
Spartan-II family.  
Higher performance  
Faster carry logic  
•
First ASIC replacement FPGA for high-volume  
production with on-chip RAM  
More flexible high-speed clock network  
Latch capability in Configurable Logic Blocks  
Input fast capture latch  
•
•
•
•
Density up to 1862 logic cells or 40,000 system gates  
Streamlined feature set based on XC4000 architecture  
System performance beyond 80 MHz  
Optional mux or 2-input function generator on outputs  
12 mA or 24 mA output drive  
5V and 3.3V PCI compliant  
Broad set of AllianceCORE™ and LogiCORE™  
predefined solutions available  
Enhanced Boundary Scan  
•
•
Unlimited reprogrammability  
Low cost  
Express Mode configuration  
Chip scale packaging  
Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays  
Max  
System  
Gates (Logic and RAM)  
Typical  
Gate Range  
Max.  
Avail. Distributed  
CLBs Flip-flops User I/O RAM Bits  
Total  
Logic  
Cells  
238  
CLB  
Matrix  
Total  
No. of  
(1)  
Device  
XCS05 and XCS05XL  
XCS10 and XCS10XL  
XCS20 and XCS20XL  
5,000  
10,000  
20,000  
30,000  
40,000  
2,000-5,000  
3,000-10,000  
7,000-20,000  
10,000-30,000  
13,000-40,000  
10 x 10  
14 x 14  
20 x 20  
24 x 24  
28 x 28  
100  
196  
400  
576  
784  
360  
616  
77  
3,200  
6,272  
466  
112  
160  
192  
224  
950  
1,120  
1,536  
2,016  
12,800  
18,432  
25,088  
XCS30 and XCS30XL 1368  
XCS40 and XCS40XL 1862  
Notes:  
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS060 (v1.6) September 19, 2001  
www.xilinx.com  
1
Product Specification  
1-800-255-7778  
1234567...82

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