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XCS05XL-4VQG100C PDF预览

XCS05XL-4VQG100C

更新时间： 2024-02-16 12:54:00
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
83页 770K
描述
Field Programmable Gate Array, 100 CLBs, 2000 Gates, 217MHz, 238-Cell, CMOS, PQFP100, PLASTIC, VQFP-100

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XCS05XL-4VQG100C 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：TFQFP, TQFP100,.63SQ
针数：100Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.78其他特性：MAXIMUM USABLE GATES 5000
最大时钟频率：217 MHzCLB-Max的组合延迟：1.1 ns
JESD-30 代码：S-PQFP-G100JESD-609代码：e3
长度：14 mm湿度敏感等级：3
可配置逻辑块数量：100等效关口数量：2000
输入次数：77逻辑单元数量：238
输出次数：77端子数量：100
最高工作温度：85 °C最低工作温度：
组织：100 CLBS, 2000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：TFQFP封装等效代码：TQFP100,.63SQ
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Field Programmable Gate Arrays
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

XCS05XL-4VQG100C 数据手册

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Spartan and Spartan-XL FPGA  
Families Data Sheet  
0
0
DS060 (v1.8) June 26, 2008  
Product Specification  
•
System level features  
Introduction  
-
-
-
-
Available in both 5V and 3.3V versions  
On-chip SelectRAM™ memory  
Fully PCI compliant  
Full readback capability for program verification  
and internal node observability  
The Spartan® and the Spartan-XL FPGA families are a  
high-volume production FPGA solution that delivers all the  
key requirements for ASIC replacement up to 40,000 gates.  
These requirements include high performance, on-chip  
RAM, core solutions and prices that, in high volume,  
approach and in many cases are equivalent to mask pro-  
grammed ASIC devices.  
-
-
-
-
-
-
Dedicated high-speed carry logic  
Internal 3-state bus capability  
Eight global low-skew clock or signal networks  
IEEE 1149.1-compatible Boundary Scan logic  
Low cost plastic packages available in all densities  
Footprint compatibility in common packages  
By streamlining the Spartan series feature set, leveraging  
advanced process technologies and focusing on total cost  
management, the Spartan series delivers the key features  
required by ASIC and other high-volume logic users while  
avoiding the initial cost, long development cycles and inher-  
ent risk of conventional ASICs. The Spartan and Spar-  
tan-XL families in the Spartan series have ten members, as  
shown in Table 1.  
•
Fully supported by powerful Xilinx ISE® Classics  
development system  
-
Fully automatic mapping, placement and routing  
Additional Spartan-XL Family Features  
Spartan/Spartan-XL FPGA Features  
•
•
•
•
•
•
•
•
•
•
•
•
•
3.3V supply for low power with 5V tolerant I/Os  
Power down input  
Note: The Spartan series devices described in this data  
sheet include the 5V Spartan family and the 3.3V  
Spartan-XL family. See the separate data sheets for more  
advanced members for the Spartan Series.  
Higher performance  
Faster carry logic  
More flexible high-speed clock network  
Latch capability in Configurable Logic Blocks  
Input fast capture latch  
Optional mux or 2-input function generator on outputs  
12 mA or 24 mA output drive  
5V and 3.3V PCI compliant  
•
First ASIC replacement FPGA for high-volume  
production with on-chip RAM  
•
•
•
•
Density up to 1862 logic cells or 40,000 system gates  
Streamlined feature set based on XC4000 architecture  
System performance beyond 80 MHz  
Broad set of AllianceCORE and LogiCORE™  
predefined solutions available  
Enhanced Boundary Scan  
Express Mode configuration  
•
•
Unlimited reprogrammability  
Low cost  
Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays  
Max  
System  
Typical  
Gate Range  
Max.  
Avail. Distributed  
CLBs Flip-flops User I/O RAM Bits  
Total  
Logic  
Cells  
238  
CLB  
Total  
No. of  
Device  
Gates (Logic and RAM)(1) Matrix  
XCS05 and XCS05XL  
XCS10 and XCS10XL  
XCS20 and XCS20XL  
5,000  
10,000  
20,000  
30,000  
40,000  
2,000-5,000  
3,000-10,000  
7,000-20,000  
10,000-30,000  
13,000-40,000  
10 x 10  
14 x 14  
20 x 20  
24 x 24  
28 x 28  
100  
196  
400  
576  
784  
360  
616  
77  
112  
3,200  
6,272  
466  
950  
1,120  
1,536  
2,016  
160  
12,800  
18,432  
25,088  
XCS30 and XCS30XL 1368  
XCS40 and XCS40XL 1862  
Notes:  
192  
205(2)  
1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM.  
2. XCS40XL provided 224 max I/O in CS280 package discontinued by PDN2004-01.  
© 1998-2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS060 (v1.8) June 26, 2008  
www.xilinx.com  
1
Product Specification  
1234567...83

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