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XCR3512XL-7PQG208C PDF预览

XCR3512XL-7PQG208C

更新时间： 2024-09-25 15:58:23
品牌 Logo 应用领域
赛灵思 - XILINX 时钟输入元件可编程逻辑
页数 文件大小 规格书
15页 218K
描述
EE PLD, 7.5ns, 512-Cell, CMOS, PQFP208, LEAD FREE, PLASTIC, QFP-208

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XCR3512XL-7PQG208C 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFP
包装说明：FQFP, QFP208,1.2SQ,20针数：208
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：12 weeks
风险等级：5.08Is Samacsys：N
其他特性：YES最大时钟频率：135 MHz
系统内可编程：YESJESD-30 代码：S-PQFP-G208
JESD-609代码：e3JTAG BST：YES
长度：28 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：180
宏单元数：512端子数量：208
最高工作温度：70 °C最低工作温度：
组织：0 DEDICATED INPUTS, 180 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：FQFP
封装等效代码：QFP208,1.2SQ,20封装形状：SQUARE
封装形式：FLATPACK, FINE PITCH峰值回流温度（摄氏度）：245
电源：3.3 V可编程逻辑类型：EE PLD
传播延迟：7.5 ns认证状态：Not Qualified
座面最大高度：4.1 mm子类别：Programmable Logic Devices
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：28 mm
Base Number Matches：1

XCR3512XL-7PQG208C 数据手册

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R
XCR3512XL: 512 Macrocell CPLD  
0
14  
DS081 (v2.0) March 31, 2006  
Product Specification  
Features  
Description  
•
•
•
•
•
Low power 3.3V 512 macrocell CPLD  
The CoolRunner™ XPLA3 XCR3512XL device is a 3.3V,  
512 macrocell CPLD targeted at power sensitive designs  
that require leading edge programmable logic solutions. A  
total of 32 function blocks provide 12,000 usable gates.  
Pin-to-pin propagation delays are as fast as 7.0 ns with a  
maximum system frequency of 135 MHz.  
7.0 ns pin-to-pin logic delays  
System frequencies up to 135 MHz  
512 macrocells with 12,000 usable gates  
Available in small footprint packages  
-
-
-
208-pin PQFP (180 user I/O)  
256-ball FBGA (212 user I/O)  
324-ball FBGA (260 user I/O)  
TotalCMOS Design Technique for Fast  
Zero Power  
•
Optimized for 3.3V systems  
CoolRunner XPLA3 CPLDs offer a TotalCMOS™ solution,  
both in process technology and design technique. This fam-  
ily employs a cascade of CMOS gates to implement its sum  
of products, instead of the traditional sense amp approach.  
This CMOS gate implementation allows Xilinx to offer  
CPLDs that are both high performance and low power,  
breaking the paradigm that to have low power, you must  
have low performance. Refer to Figure 1 and Table 1 show-  
ing the ICC vs. Frequency of our XCR3512XL TotalCMOS  
CPLD (data taken with 32 resetable up/down, 16-bit  
counters at 3.3V, 25°C).  
-
-
-
-
Ultra low power operation  
Typical Standby Current of 18 μA at 25°C  
5V tolerant I/O pins with 3.3V core supply  
Advanced 0.35 micron five layer metal EEPROM  
process  
Fast Zero Power™ (FZP) CMOS design  
technology  
3.3V PCI electrical specification compatible outputs  
(no internal clamp diode on any input or I/O)  
-
-
•
Advanced system features  
-
-
-
-
-
-
-
-
In-system programming  
Input registers  
Predictable timing model  
Up to 23 clocks available per function block  
Excellent pin retention during design changes  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
Four global clocks  
300  
270  
240  
210  
180  
150  
Eight product term control terms per function block  
•
•
•
Fast ISP programming times  
Port Enable pin for additional I/O  
120  
90  
2.7V to 3.6V supply voltage at industrial grade voltage  
range  
•
•
•
Programmable slew rate control per output  
Security bit prevents unauthorized access  
60  
30  
Refer to the CoolRunner™ XPLA3 family data sheet  
(DS012) for architecture description  
0
20  
40  
60  
80  
100  
120  
Frequency (MHz)  
Figure 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C  
Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C  
Frequency (MHz)  
0
1
10  
20  
40  
60  
80  
100  
120  
Typical ICC (mA)  
0.018  
2.57  
25.5  
50.8  
100.3  
147.9  
193.5  
237.8  
281.6  
© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS081 (v2.0) March 31, 2006  
www.xilinx.com  
1
Product Specification  
 
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XCR3512XL-7PQG208C 替代型号

型号 品牌 替代类型 描述 数据表
XCR3512XL-10PQG208C XILINX

完全替代

 EE PLD, 10ns, 512-Cell, CMOS, PQFP208, LEAD FREE, PLASTIC, QFP-208
XCR3512XL-12PQ208C XILINX

完全替代

 XCR3512XL: 512 Macrocell CPLD
XCR3512XL-10PQ208C XILINX

完全替代

 XCR3512XL: 512 Macrocell CPLD

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