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XC7V2000T-L2FLG1925E PDF预览

XC7V2000T-L2FLG1925E

更新时间: 2024-02-05 23:06:51
品牌 Logo 应用领域
赛灵思 - XILINX 时钟可编程逻辑
页数 文件大小 规格书
78页 1017K
描述
Field Programmable Gate Array, 152700 CLBs, 1818MHz, 1954560-Cell, CMOS, PBGA1925, FBGA-1925

XC7V2000T-L2FLG1925E 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:BGA, BGA1924,44X44,40Reach Compliance Code:not_compliant
ECCN代码:3A001.A.7.AHTS代码:8542.39.00.01
风险等级:5.8最大时钟频率:1818 MHz
CLB-Max的组合延迟:0.61 nsJESD-30 代码:S-PBGA-B1925
JESD-609代码:e1长度:45 mm
可配置逻辑块数量:152700输入次数:1200
逻辑单元数量:1954560输出次数:1200
端子数量:1925组织:152700 CLBS
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA1924,44X44,40封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):NOT SPECIFIED
电源:1,1.8 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:3.75 mm
子类别:Field Programmable Gate Arrays最大供电电压:1.03 V
最小供电电压:0.97 V标称供电电压:1 V
表面贴装:YES技术:CMOS
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:45 mm
Base Number Matches:1

XC7V2000T-L2FLG1925E 数据手册

 浏览型号XC7V2000T-L2FLG1925E的Datasheet PDF文件第2页浏览型号XC7V2000T-L2FLG1925E的Datasheet PDF文件第3页浏览型号XC7V2000T-L2FLG1925E的Datasheet PDF文件第4页浏览型号XC7V2000T-L2FLG1925E的Datasheet PDF文件第5页浏览型号XC7V2000T-L2FLG1925E的Datasheet PDF文件第6页浏览型号XC7V2000T-L2FLG1925E的Datasheet PDF文件第7页 
Virtex-7 T and XT FPGAs Data Sheet:  
DC and AC Switching Characteristics  
DS183 (v1.27) April 6, 2017  
Product Specification  
Introduction  
Virtex®-7 T and XT FPGAs are available in -3, -2, -1, and  
-2L speed grades, with -3 having the highest performance.  
device are the same as for a -1C speed grade commercial  
device). However, only selected speed grades and/or  
devices are available in each temperature range.  
The -2L devices operate at V  
= 1.0V and are screened  
CCINT  
for lower maximum static power. The speed specification of  
a -2L device is the same as the -2 speed grade. The -2G  
speed grade is available in devices utilizing Stacked Silicon  
Interconnect (SSI) technology. The -2G speed grade  
supports 12.5 Gb/s GTX or 13.1 Gb/s GTH transceivers as  
well as the standard -2 speed grade specifications.  
All supply voltage and junction temperature specifications  
are representative of worst-case conditions. The parameters  
included are common to popular designs and typical  
applications.  
Available device and package combinations can be found in  
:
Virtex-7 T and XT FPGA DC and AC characteristics are  
specified in commercial, extended, industrial, and military  
temperature ranges. Except for the operating temperature  
range or unless otherwise noted, all the DC and AC electrical  
parameters are the same for a particular speed grade (that  
is, the timing characteristics of a -1M speed grade military  
7 Series FPGAs Overview (DS180)  
Defense-Grade 7 Series FPGAs Overview (DS185)  
This Virtex-7 T and XT FPGA data sheet, part of an overall  
set of documentation on the 7 series FPGAs, is available on  
the Xilinx website at www.xilinx.com/7.  
DC Characteristics  
Table 1: Absolute Maximum Ratings  
(1)  
Symbol  
FPGA Logic  
VCCINT  
Description  
Min  
Max  
Units  
Internal supply voltage  
Auxiliary supply voltage  
–0.5  
–0.5  
1.1  
2.0  
V
V
V
V
V
V
V
V
V
V
VCCAUX  
VCCBRAM  
Supply voltage for the block RAM memories  
Output drivers supply voltage for 3.3V HR I/O banks  
Output drivers supply voltage for 1.8V HP I/O banks  
Auxiliary supply voltage  
–0.5  
1.1  
–0.5  
3.6  
VCCO  
–0.5  
2.0  
VCCAUX_IO  
VREF  
–0.5  
2.06  
Input reference voltage  
–0.5  
2.0  
–0.40  
–0.55  
–0.40  
I/O input voltage for 3.3V HR I/O banks  
I/O input voltage for 1.8V HP I/O banks  
VCCO + 0.55  
V
CCO + 0.55  
2.625  
(2)(3)(4)  
VIN  
I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except  
TMDS_33(5)  
VCCBATT  
Key memory battery backup supply  
–0.5  
2.0  
V
GTX and GTH Transceivers  
VMGTAVCC  
Analog supply voltage for the GTX/GTH transmitter and receiver circuits  
–0.5  
–0.5  
–0.5  
–0.5  
1.1  
1.32  
1.935  
1.32  
V
V
V
V
VMGTAVTT  
Analog supply voltage for the GTX/GTH transmitter and receiver termination circuits  
Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX/GTH transceivers  
GTX/GTH transceiver reference clock absolute input voltage  
VMGTVCCAUX  
VMGTREFCLK  
© 2011–2017 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Kintex, Artix, Zynq, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in the  
United States and other countries. All other trademarks are the property of their respective owners.  
DS183 (v1.27) April 6, 2017  
www.xilinx.com  
Product Specification  
1
 
 
 

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