Datasheet > XC5VLX110-3FFG1153C

XC5VLX110-3FFG1153C

更新时间： 2024-02-05 09:36:56

品牌	Logo	应用领域
赛灵思 - XILINX		时钟栅可编程逻辑
页数	文件大小	规格书
13页	160K
描述
Field Programmable Gate Array, 8640 CLBs, 1412MHz, 110592-Cell, CMOS, PBGA1153, 35 X 35 MM, LEAD FREE, FBGA-1153

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技术参数
数据手册
替代型号

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XC5VLX110-3FFG1153C 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	BGA	包装说明：	BGA, BGA1153,34X34,40
针数：	1153	Reach Compliance Code：	not_compliant
ECCN代码：	3A001.A.7.A	HTS代码：	8542.39.00.01
风险等级：	1.58	最大时钟频率：	1412 MHz
JESD-30 代码：	S-PBGA-B1153	JESD-609代码：	e1
长度：	35 mm	湿度敏感等级：	4
可配置逻辑块数量：	8640	输入次数：	800
逻辑单元数量：	110592	输出次数：	800
端子数量：	1153	最高工作温度：	85 °C
最低工作温度：		组织：	8640 CLBS
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA1153,34X34,40	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	245
电源：	1,2.5 V	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	座面最大高度：	3.4 mm
子类别：	Field Programmable Gate Arrays	最大供电电压：	1.05 V
最小供电电压：	0.95 V	标称供电电压：	1 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子面层：	Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	35 mm	Base Number Matches：	1

XC5VLX110-3FFG1153C 数据手册

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Virtex-5 Family Overview

DS100 (v5.0) February 6, 2009

Product Specification

General Description

The Virtex®-5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL™ (Advanced

Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice

offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic

designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks,

including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-

controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles

with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options.

Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity,

PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance

PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of

performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5

FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength

of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP

designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and

connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and

link/transaction layer capability.

Summary of Virtex-5 FPGA Features

•

Five platforms LX, LXT, SXT, TXT, and FXT

•

Advanced DSP48E slices

−

Virtex-5 LX: High-performance general logic applications

Virtex-5 LXT: High-performance logic with advanced serial

connectivity

Virtex-5 SXT: High-performance signal processing

applications with advanced serial connectivity

Virtex-5 TXT: High-performance systems with double

density advanced serial connectivity

−

25 x 18, two’s complement, multiplication

−

Optional adder, subtracter, and accumulator

−

Optional pipelining

Optional bitwise logical functionality

Dedicated cascade connections

−

•

Flexible configuration options

−

SPI and Parallel FLASH interface

Multi-bitstream support with dedicated fallback

reconfiguration logic

Virtex-5 FXT: High-performance embedded systems with

advanced serial connectivity

•

Cross-platform compatibility

−

Auto bus width detection capability

LXT, SXT, and FXT devices are footprint compatible in the

same package using adjustable voltage regulators

•

System Monitoring capability on all devices

−

On-chip/Off-chip thermal monitoring

On-chip/Off-chip power supply monitoring

JTAG access to all monitored quantities

Most advanced, high-performance, optimal-utilization,

FPGA fabric

−

Real 6-input look-up table (LUT) technology

Dual 5-LUT option

Improved reduced-hop routing

64-bit distributed RAM option

SRL32/Dual SRL16 option

Integrated Endpoint blocks for PCI Express Designs

−

LXT, SXT, TXT, and FXT Platforms

Compliant with the PCI Express Base Specification 1.1

x1, x4, or x8 lane support per block

Works in conjunction with RocketIO™ transceivers

•

Powerful clock management tile (CMT) clocking

−

•

Tri-mode 10/100/1000 Mb/s Ethernet MACs

Digital Clock Manager (DCM) blocks for zero delay

buffering, frequency synthesis, and clock phase shifting

PLL blocks for input jitter filtering, zero delay buffering,

frequency synthesis, and phase-matched clock division

−

LXT, SXT, TXT, and FXT Platforms

−

RocketIO transceivers can be used as PHY or connect to

external PHY using many soft MII (Media Independent

Interface) options

−

•

RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s

LXT and SXT Platforms

RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s

TXT and FXT Platforms

PowerPC 440 Microprocessors

36-Kbit block RAM/FIFOs

−

True dual-port RAM blocks

Enhanced optional programmable FIFO logic

Programmable

−

True dual-port widths up to x36

Simple dual-port widths up to x72

−

FXT Platform only

RISC architecture

−

Built-in optional error-correction circuitry

Optionally program each block as two independent 18-Kbit

blocks

7-stage pipeline

32-Kbyte instruction and data caches included

Optimized processor interface structure (crossbar)

•

High-performance parallel SelectIO technology

•

65-nm copper CMOS process technology

1.0V core voltage

−

1.2 to 3.3V I/O Operation

Source-synchronous interfacing using ChipSync™

technology

High signal-integrity flip-chip packaging available in standard

or Pb-free package options

−

Digitally-controlled impedance (DCI) active termination

Flexible fine-grained I/O banking

High-speed memory interface support

countries. PowerPC is a trademark of IBM Corp. and is used under license. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property

of their respective owners.

DS100 (v5.0) February 6, 2009

www.xilinx.com

Product Specification

12 3 4 5 6 7...13

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XC5VLX110-3FFG1153C 替代型号

型号	品牌	替代类型	描述	数据表
XC5VLX110-1FFG1153C	XILINX	类似代替	Field Programmable Gate Array, 8640 CLBs, 1098MHz, 110592-Cell, CMOS, PBGA1153, 35 X 35 MM

与XC5VLX110-3FFG1153C相关器件

型号	品牌	获取价格	描述	数据表
XC5VLX110T	XILINX	获取价格	Virtex-5 Family Overview
XC5VLX110T-1FF1136C	XILINX	获取价格	Field Programmable Gate Array, 8640 CLBs, 1098MHz, 110592-Cell, CMOS, PBGA1136, 35 X 35 MM
XC5VLX110T-1FF1136I	XILINX	获取价格	Field Programmable Gate Array, 8640 CLBs, 1098MHz, 110592-Cell, CMOS, PBGA1136, 35 X 35 MM
XC5VLX110T-1FF1738I	XILINX	获取价格	Field Programmable Gate Array, 8640 CLBs, 1098MHz, 110592-Cell, CMOS, PBGA1738, 42.50 X 42
XC5VLX110T-1FFG1136C	XILINX	获取价格	Field Programmable Gate Array, 8640 CLBs, 1098MHz, 110592-Cell, CMOS, PBGA1136, 35 X 35 MM
XC5VLX110T-1FFG1136I	XILINX	获取价格	Field Programmable Gate Array, 8640 CLBs, 1098MHz, 110592-Cell, CMOS, PBGA1136, 35 X 35 MM
XC5VLX110T-2FF1136I	XILINX	获取价格	Field Programmable Gate Array, 8640 CLBs, 1265MHz, 110592-Cell, CMOS, PBGA1136, 35 X 35 MM
XC5VLX110T-2FF1738I	XILINX	获取价格	Field Programmable Gate Array, 8640 CLBs, 1265MHz, 110592-Cell, CMOS, PBGA1738, 42.50 X 42
XC5VLX110T-2FFG1136I	XILINX	获取价格	Field Programmable Gate Array, 8640 CLBs, 1265MHz, 110592-Cell, CMOS, PBGA1136, 35 X 35 MM
XC5VLX110T-2FFG1738I	XILINX	获取价格	Field Programmable Gate Array, 8640 CLBs, 1265MHz, 110592-Cell, CMOS, PBGA1738, 42.50 X 42

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