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XC3S100E-4TQG144IS1 PDF预览

XC3S100E-4TQG144IS1

更新时间: 2024-11-23 15:58:15
品牌 Logo 应用领域
赛灵思 - XILINX 时钟可编程逻辑
页数 文件大小 规格书
227页 6371K
描述
Field Programmable Gate Array, 240 CLBs, 100000 Gates, 572MHz, 2160-Cell, CMOS, PQFP144, 22 X 22 MM, 1.60 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, TQFP-144

XC3S100E-4TQG144IS1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:PGA
包装说明:LFQFP, QFP144,.87SQ,20针数:144
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.25最大时钟频率:572 MHz
CLB-Max的组合延迟:0.76 nsJESD-30 代码:S-PQFP-G144
JESD-609代码:e3长度:20 mm
湿度敏感等级:3可配置逻辑块数量:240
等效关口数量:100000输入次数:108
逻辑单元数量:2160输出次数:80
端子数量:144最高工作温度:100 °C
最低工作温度:-40 °C组织:240 CLBS, 100000 GATES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP144,.87SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:1.2,1.2/3.3,2.5 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Field Programmable Gate Arrays最大供电电压:1.26 V
最小供电电压:1.14 V标称供电电压:1.2 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:20 mmBase Number Matches:1

XC3S100E-4TQG144IS1 数据手册

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1
Spartan-3E FPGA Family  
Data Sheet  
DS312 July 19, 2013  
Product Specification  
Module 1:  
Introduction and Ordering Information  
Module 3:  
DC and Switching Characteristics  
DS312 (v4.1) July 19, 2013  
DS312 (v4.1) July 19, 2013  
Introduction  
DC Electrical Characteristics  
Features  
Absolute Maximum Ratings  
Supply Voltage Specifications  
Recommended Operating Conditions  
DC Characteristics  
Architectural Overview  
Package Marking  
Ordering Information  
Switching Characteristics  
Module 2:  
I/O Timing  
Functional Description  
SLICE Timing  
DS312 (v4.1) July 19, 2013  
DCM Timing  
Input/Output Blocks (IOBs)  
Block RAM Timing  
Multiplier Timing  
Configuration and JTAG Timing  
Overview  
SelectIO™ Signal Standards  
Configurable Logic Block (CLB)  
Block RAM  
Module 4:  
Pinout Descriptions  
DS312 (v4.1) July 19, 2013  
Dedicated Multipliers  
Digital Clock Manager (DCM)  
Clock Network  
Pin Descriptions  
Package Overview  
Pinout Tables  
Configuration  
Powering Spartan®-3E FPGAs  
Production Stepping  
Footprint Diagrams  
© Copyright 2005–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx  
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.  
DS312 July 19, 2013  
www.xilinx.com  
Product Specification  
1

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