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XC3142A1VQ100C PDF预览

XC3142A1VQ100C

更新时间: 2024-11-17 15:58:15
品牌 Logo 应用领域
赛灵思 - XILINX 时钟可编程逻辑
页数 文件大小 规格书
76页 814K
描述
Field Programmable Gate Array, 144 CLBs, 2000 Gates, 323MHz, 144-Cell, CMOS, PQFP100, PLASTIC, VQFP-100

XC3142A1VQ100C 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:TFQFP, TQFP100,.63SQ针数:100
Reach Compliance Code:compliant风险等级:5.84
其他特性:MAX USABLE 3000 LOGIC GATES最大时钟频率:323 MHz
CLB-Max的组合延迟:1.75 nsJESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
湿度敏感等级:3可配置逻辑块数量:144
等效关口数量:2000输入次数:82
逻辑单元数量:144输出次数:82
端子数量:100最高工作温度:85 °C
最低工作温度:组织:144 CLBS, 2000 GATES
封装主体材料:PLASTIC/EPOXY封装代码:TFQFP
封装等效代码:TQFP100,.63SQ封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):245
电源:5 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Field Programmable Gate Arrays最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

XC3142A1VQ100C 数据手册

 浏览型号XC3142A1VQ100C的Datasheet PDF文件第2页浏览型号XC3142A1VQ100C的Datasheet PDF文件第3页浏览型号XC3142A1VQ100C的Datasheet PDF文件第4页浏览型号XC3142A1VQ100C的Datasheet PDF文件第5页浏览型号XC3142A1VQ100C的Datasheet PDF文件第6页浏览型号XC3142A1VQ100C的Datasheet PDF文件第7页 
Product Obsolete or Under Obsolescence  
0
XC3000 Series  
R
Field Programmable Gate Arrays  
(XC3000A/L, XC3100A/L)  
0
7*  
November 9, 1998 (Version 3.1)  
Product Description  
Complete Development System  
Features  
-
-
-
-
-
Schematic capture, automatic place and route  
Logic and timing simulation  
Interactive design editor for design optimization  
Timing calculator  
Interfaces to popular design environments like  
Viewlogic, Cadence, Mentor Graphics, and others  
Complete line of four related Field Programmable Gate  
Array product families  
-
XC3000A, XC3000L, XC3100A, XC3100L  
Ideal for a wide range of custom VLSI design tasks  
-
-
Replaces TTL, MSI, and other PLD logic  
Integrates complete sub-systems into a single  
package  
Additional XC3100A Features  
-
Avoids the NRE, time delay, and risk of conventional  
masked gate arrays  
Ultra-high-speed FPGA family with six members  
-
-
-
50-85 MHz system clock rates  
190 to 370 MHz guaranteed flip-flop toggle rates  
1.55 to 4.1 ns logic delays  
High-performance CMOS static memory technology  
-
Guaranteed toggle rates of 70 to 370 MHz, logic  
delays from 7 to 1.5 ns  
High-end additional family member in the 22 X 22 CLB  
array-size XC3195A device  
8 mA output sink current and 8 mA source current  
Maximum power-down and quiescent current is 5 mA  
100% architecture and pin-out compatible with other  
XC3000 families  
-
-
System clock speeds over 85 MHz  
Low quiescent and active power consumption  
Flexible FPGA architecture  
-
-
Compatible arrays ranging from 1,000 to 7,500 gate  
complexity  
Extensive register, combinatorial, and I/O  
capabilities  
7
Software and bitstream compatible with the XC3000,  
XC3000A, and XC3000L families  
-
-
-
-
High fan-out signal distribution, low-skew clock nets  
Internal 3-state bus capabilities  
TTL or CMOS input thresholds  
On-chip crystal oscillator amplifier  
XC3100A combines the features of the XC3000A and  
XC3100 families:  
Additional interconnect resources for TBUFs and CE  
inputs  
Error checking of the configuration bitstream  
Soft startup holds all outputs slew-rate limited during  
initial power-up  
Unlimited reprogrammability  
-
-
Easy design iteration  
In-system logic changes  
Extensive packaging options  
-
-
Over 20 different packages  
Plastic and ceramic surface-mount and pin-grid-  
array packages  
More advanced CMOS process  
Low-Voltage Versions Available  
-
Thin and Very Thin Quad Flat Pack (TQFP and  
VQFP) options  
Low-voltage devices function at 3.0 - 3.6 V  
XC3000L - Low-voltage versions of XC3000A devices  
XC3100L - Low-voltage versions of XC3100A devices  
Ready for volume production  
-
-
-
Standard, off-the-shelf product availability  
100% factory pre-tested devices  
Excellent reliability record  
Max Logic Typical Gate  
User I/Os  
Max  
Horizontal Configuration  
Device  
CLBs Array  
64 8 x 8  
Flip-Flops  
Gates  
1,500  
2,000  
3,000  
4,500  
6,000  
7,500  
Range  
Longlines  
Data Bits  
14,779  
22,176  
30,784  
46,064  
64,160  
94,984  
XC3020A, 3020L, 3120A  
XC3030A, 3030L, 3130A  
XC3042A, 3042L, 3142A, 3142L  
XC3064A, 3064L, 3164A  
XC3090A, 3090L, 3190A, 3190L  
XC3195A  
1,000 - 1,500  
64  
80  
256  
360  
16  
20  
24  
32  
40  
44  
1,500 - 2,000 100 10 x 10  
2,000 - 3,000 144 12 x 12  
3,500 - 4,500 224 16 x 14  
5,000 - 6,000 320 16 x 20  
6,500 - 7,500 484 22 x 22  
96  
480  
120  
144  
176  
688  
928  
1,320  
November 9, 1998 (Version 3.1)  
7-3  

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