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XA6SLX75-2CSG484Q PDF预览

XA6SLX75-2CSG484Q

更新时间: 2024-01-28 20:35:25
品牌 Logo 应用领域
赛灵思 - XILINX 可编程逻辑
页数 文件大小 规格书
10页 288K
描述
Field Programmable Gate Array,

XA6SLX75-2CSG484Q 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:,Reach Compliance Code:compliant
ECCN代码:3A991.DHTS代码:8542.39.00.01
Factory Lead Time:12 weeks风险等级:5.59
JESD-609代码:e1湿度敏感等级:3
峰值回流温度(摄氏度):260可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
端子面层:TIN SILVER COPPER处于峰值回流温度下的最长时间:30
Base Number Matches:1

XA6SLX75-2CSG484Q 数据手册

 浏览型号XA6SLX75-2CSG484Q的Datasheet PDF文件第1页浏览型号XA6SLX75-2CSG484Q的Datasheet PDF文件第2页浏览型号XA6SLX75-2CSG484Q的Datasheet PDF文件第3页浏览型号XA6SLX75-2CSG484Q的Datasheet PDF文件第5页浏览型号XA6SLX75-2CSG484Q的Datasheet PDF文件第6页浏览型号XA6SLX75-2CSG484Q的Datasheet PDF文件第7页 
XA Spartan-6 Automotive FPGA Family Overview  
SLICEL  
One quarter (25%) of the XA Spartan-6 FPGA slices are SLICELs, which contain all the features of the SLICEM except the  
memory/shift register function.  
SLICEX  
One half (50%) of the XA Spartan-6 FPGA slices are SLICEXs. The SLICEXs have the same structure as SLICELs except  
the arithmetic carry option and the wide multiplexers.  
Clock Management  
Each XA Spartan-6 FPGA has up to six CMTs, each consisting of two DCMs and one PLL, which can be used individually  
or cascaded.  
DCM  
The DCM provides four phases of the input frequency (CLKIN): shifted 0°, 90°, 180°, and 270° (CLK0, CLK90, CLK180, and  
CLK270). It also provides a doubled frequency CLK2X and its complement CLK2X180. The CLKDV output provides a  
fractional clock frequency that can be phase-aligned to CLK0. The fraction is programmable as every integer from 2 to 16,  
as well as 1.5, 2.5, 3.5 . . . 7.5. CLKIN can optionally be divided by 2. The DCM can be a zero-delay clock buffer when a clock  
signal drives CLKIN, while the CLK0 output is fed back to the CLKFB input.  
Frequency Synthesis  
Independent of the basic DCM functionality, the frequency synthesis outputs CLKFX and CLKFX180 can be programmed to  
generate any output frequency that is the DCM input frequency (F ) multiplied by M and simultaneously divided by D, where  
IN  
M can be any integer from 2 to 32 and D can be any integer from 1 to 32.  
Phase Shifting  
With CLK0 connected to CLKFB, all nine CLK outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV,  
CLKFX, and CLKFX180) can be shifted by a common amount, defined as any integer multiple of a fixed delay. A fixed DCM  
delay value (fraction of the input period) can be established by configuration and can also be incremented or decremented  
dynamically.  
Spread-Spectrum Clocking  
The DCM can accept and track typical spread-spectrum clock inputs, provided they abide by the input clock specifications  
listed in the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics. XA Spartan-6 FPGAs can generate a spread-  
spectrum clock source from a standard fixed-frequency oscillator.  
PLL  
The PLL can serve as a frequency synthesizer for a wider range of frequencies and as a jitter filter for incoming clocks in  
conjunction with the DCMs. The heart of the PLL is a voltage-controlled oscillator (VCO) with a frequency range of  
400 MHz to 1,080 MHz, thus spanning more than one octave. Three sets of programmable frequency dividers (D, M, and O)  
adapt the VCO to the required application.  
The pre-divider D (programmable by configuration) reduces the input frequency and feeds one input of the traditional PLL  
phase comparator. The feedback divider (programmable by configuration) acts as a multiplier because it divides the VCO  
output frequency before feeding the other input of the phase comparator. D and M must be chosen appropriately to keep the  
VCO within its controllable frequency range.  
The VCO has eight equally spaced outputs (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each can be selected to drive  
one of the six output dividers, O0 to O5 (each programmable by configuration to divide by any integer from 1 to 128).  
DS170 (v1.3) December 13, 2012  
www.xilinx.com  
Product Specification  
4
 
 

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