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XA Artix-7 FPGAs Data Sheet: Overview
DS197 (v1.3) November 15, 2017
Product Specification
General Description
Xilinx® XA Artix®-7 (Automotive) FPGAs are optimized for the lowest cost and power with small form-factor packaging for high-volume automotive
applications. Designers can leverage more logic per watt compared to the Spartan®-6 family.
Built on a state-of-the-art high-performance/low-power (HPL) 28 nm high-k metal gate (HKMG) process technology, XA Artix-7 FPGAs redefine low-cost
alternatives with more logic per watt. Unparalleled increase in system performance with 52 Gb/s I/O bandwidth, 100,000 logic cell capacity, 264 GMAC/s
DSP, and flexible built-in DDR3 memory interfaces enable a new class of high-throughput, low-cost automotive applications. XA Artix-7 FPGAs also offer
many high-end features, such as integrated advanced Analog Mixed Signal (AMS) technology. Analog becomes the next level of integration through the
seamless implementation of independent dual 12-bit, 1 MSPS, 17-channel analog-to-digital converters. Most importantly, XA Artix-7 FPGAs proudly meet
the high standards of the automotive grade with a maximum temperature of 125°C.
Summary of XA Artix-7 FPGA Features
•
Automotive Temperatures:
•
•
A user configurable analog interface (XADC), incorporating dual
12-bit 1MSPS analog-to-digital converters with on-chip thermal and
supply sensors.
Single-ended and differential I/O standards with speeds of up to
1.25 Gb/s
•
•
I-Grade: Tj= –40°C to +100°C
Q-Grade: Tj= –40°C to +125°C
•
Automotive Standards:
•
•
•
•
ISO-TS16949 compliant
AEC-Q100 qualification
Production Part Approval Process (PPAP) documentation
Beyond AEC-Q100 qualification is available upon request
•
•
240 DSP48E1 slices with up to 264 GMACs of signal processing
Powerful clock management tiles (CMT), combining phase-locked
loop (PLL) and mixed-mode clock manager (MMCM) blocks for high
precision and low jitter
Integrated block for PCI Express® (PCIe®), for up to x4 Gen2
Endpoint
Wide variety of configuration options, including support for
commodity memories, 256-bit AES encryption with HMAC/SHA-256
authentication, and built-in SEU detection and correction
Low-cost wire-bond packaging, offering easy migration between
family members in the same package, all packages available Pb-free
Designed for high performance and lowest power with 28 nm,
HKMG, HPL process, 1.0V core voltage process technology
Strong automotive-specific third-party ecosystem with IP,
development boards, and design services
•
•
•
•
Advanced high-performance FPGA logic based on real 6-input look-
up table (LUT) technology configurable as distributed memory
36 Kb dual-port block RAM with built-in FIFO logic for on-chip data
buffering
Sub-watt performance in 100,000 logic cells
High-performance SelectIO™ technology with support for DDR3
interfaces up to 800 Mb/s
•
•
•
•
•
•
High-speed serial connectivity with built-in serial transceivers from
500 Mb/s to maximum rates of 6.25 Gb/s, enabling 50 Gb/s peak
bandwidth (full duplex)
XA Artix-7 FPGA Summary Tables
Table 1: XA Artix-7 FPGA Device-Feature Table
Configurable Logic
(3)
Block RAM Blocks
Blocks (CLBs)
Logic
Cells
DSP48E1
XADC
Blocks
Total I/O
Max User
(4)
(5)
Device
CMTs
PCIe
GTPs
(2)
(6)
(7)
Max
Distributed
RAM (Kb)
Slices
Banks
I/O
Max
(Kb)
(1)
Slices
18 Kb 36 Kb
XA7A12T
XA7A15T
XA7A25T
XA7A35T
XA7A50T
XA7A75T
12,800
16,640
23,360
33,280
52,160
75,520
2,000
2,600
3,650
5,200
8,150
171
200
40
45
40
50
20
25
720
3
5
3
5
5
6
6
1
1
1
1
1
1
1
2
4
4
4
4
4
4
1
1
1
1
1
1
1
3
5
3
5
5
6
6
150
210
150
210
210
285
285
900
313
80
90
45
1,620
1,800
2,700
3,780
4,860
400
90
100
150
210
270
50
600
120
180
240
75
11,800
15,850
892
105
135
XA7A100T 101,440
1,188
Notes:
1.
2.
3.
4.
5.
6.
7.
Each 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.
Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator.
Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb blocks.
Each CMT contains one MMCM and one PLL.
XA Artix-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2.
Does not include configuration Bank 0.
This number does not include GTP transceivers.
© Copyright 2014–2017 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, UltraScale, Virtex, Vivado, Zynq, and other designated brands included herein are
trademarks of Xilinx in the United States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the
property of their respective owners.
DS197 (v1.3) November 15, 2017
www.xilinx.com
Product Specification
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