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XA95144XL-15CSG144I PDF预览

XA95144XL-15CSG144I

更新时间： 2024-02-03 20:56:44
品牌 Logo 应用领域
赛灵思 - XILINX 输入元件可编程逻辑
页数 文件大小 规格书
11页 234K
描述
Flash PLD, 15.5ns, CMOS, PBGA144, CSP-144

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XA95144XL-15CSG144I 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：BGA包装说明：BGA,
针数：144Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.55JESD-30 代码：S-PBGA-B144
JESD-609代码：e1长度：12 mm
湿度敏感等级：3专用输入次数：
I/O 线路数量：117端子数量：144
最高工作温度：85 °C最低工作温度：-40 °C
组织：0 DEDICATED INPUTS, 117 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：260可编程逻辑类型：FLASH PLD
传播延迟：15.5 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：12 mmBase Number Matches：1

XA95144XL-15CSG144I 数据手册

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R
XA95144XL Automotive CPLD  
0
0
DS600 (v1.1) April 3, 2007  
Product Specification  
gates with propagation delays of 15.5 ns. See Figure 2 for  
overview.  
Features  
•
AEC-Q100 device qualification and full PPAP support  
available in I-grade.  
Power Estimation  
Power dissipation in CPLDs can vary substantially depend-  
ing on the system frequency, design application and output  
loading. Each macrocell in an XA9500XL automotive device  
must be configured for low-power mode (default mode for  
XA9500XL devices). In addition, unused product-terms and  
macrocells are automatically deactivated by the software to  
further conserve power.  
•
Guaranteed to meet full electrical specifications over  
TA = -40° C to +85° C (I-grade)  
15.5 ns pin-to-pin logic delays  
System frequency up to 64.5 MHz  
144 macrocells with 3,200 usable gates  
Available in the following package  
•
•
•
•
-
144-CSP (117 user I/O pins)  
For a general estimate of ICC, the following equation may be  
used:  
-
Pb-free package only  
•
Optimized for high-performance 3.3V systems  
-
-
Low power operation  
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V  
signals  
3.3V or 2.5V output capability  
Advanced 0.35 micron feature size CMOS  
Fast FLASH™ technology  
I
CC(mA) = MC(0.052*PT + 0.272) + 0.04 * MCTOG * MC * f  
where:  
MC = # macrocells  
-
-
PT = average number product terms per macrocell  
f = maximum clock frequency  
•
Advanced system features  
-
-
In-system programmable  
MCTOG = average % of flip-flops toggling per clock  
(~12%)  
Superior pin-locking and routability with  
Fast CONNECT™ II switch matrix  
Extra wide 54-input Function Blocks  
Up to 90 product-terms per macrocell with  
individual product-term allocation  
Local clock inversion with three global and one  
product-term clocks  
Individual output enable per output pin with local  
inversion  
Input hysteresis on all user and boundary-scan pin  
inputs  
This calculation was derived from laboratory measurements  
of an XA9500XL part filled with 16-bit counters and allowing  
a single output (the LSB) to be enabled. The actual ICC  
value varies with the design application and should be veri-  
fied during normal system operation. Figure 1 shows the  
above estimation in a graphical form. For a more detailed  
discussion of power consumption in this device, see Xilinx  
application note XAPP114, “Understanding XC9500XL  
CPLD Power.”  
-
-
-
-
-
-
-
Bus-hold circuitry on all user pin inputs  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
150  
•
•
•
•
Fast concurrent programming  
Slew rate control on individual outputs  
Enhanced data security features  
Excellent quality and reliability  
100  
64.4 MHz  
50  
0
-
Endurance exceeding 10,000 program/erase  
cycles  
-
-
20 year data retention  
ESD protection exceeding 2,000V  
100  
DS600_01_121106  
50  
Clock Frequency (MHz)  
Figure 1: Typical ICC vs. Frequency for XA95144XL  
WARNING: Programming temperature range of  
TA = 0° C to +70° C  
Description  
The XA95144XL is a 3.3V CPLD targeted for high-perfor-  
mance, low-voltage automotive applications. It is comprised  
of eight 54V18 Function Blocks, providing 3,200 usable  
© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS600 (v1.1) April 3, 2007  
www.xilinx.com  
1
Product Specification  
 
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