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XA6SLX16-2CSG324C PDF预览

XA6SLX16-2CSG324C

更新时间: 2024-02-21 21:29:33
品牌 Logo 应用领域
赛灵思 - XILINX 可编程逻辑
页数 文件大小 规格书
89页 1903K
描述
Field Programmable Gate Array,

XA6SLX16-2CSG324C 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:,Reach Compliance Code:compliant
风险等级:5.8JESD-609代码:e1
湿度敏感等级:3峰值回流温度(摄氏度):260
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY端子面层:TIN SILVER COPPER
处于峰值回流温度下的最长时间:30Base Number Matches:1

XA6SLX16-2CSG324C 数据手册

 浏览型号XA6SLX16-2CSG324C的Datasheet PDF文件第1页浏览型号XA6SLX16-2CSG324C的Datasheet PDF文件第2页浏览型号XA6SLX16-2CSG324C的Datasheet PDF文件第4页浏览型号XA6SLX16-2CSG324C的Datasheet PDF文件第5页浏览型号XA6SLX16-2CSG324C的Datasheet PDF文件第6页浏览型号XA6SLX16-2CSG324C的Datasheet PDF文件第7页 
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics  
(1)  
Table 2: Recommended Operating Conditions  
Symbol  
Description  
-3, -3N, -2  
Min  
1.14  
1.2  
Typ  
1.2  
1.23  
1.0  
2.5  
3.3  
Max  
1.26  
Units  
V
Standard performance(2)  
Extended performance(2)  
Standard performance(2)  
VCCINT  
Internal supply voltage relative to GND -3, -2  
-1L  
1.26  
V
0.95  
2.375  
3.15  
1.1  
1.05  
V
V
CCAUX = 2.5V(5)  
2.625  
3.45  
V
(3)(4)  
VCCAUX  
Auxiliary supply voltage relative to GND  
Output supply voltage relative to GND  
VCCAUX = 3.3V  
V
(6)(7)(8)  
VCCO  
3.45  
V
Commercial temperature (C) –0.5  
4.0  
V
All I/O  
standards  
(except PCI)  
Industrial temperature (I)  
Expanded (Q) temperature  
–0.5  
–0.5  
–0.5  
3.95  
V
VIN  
Input voltage relative to GND  
3.95  
V
PCI I/O standard(9)  
VCCO + 0.5  
V
Maximum current through pin using PCI I/O standard  
when forward biasing the clamp diode.(9)  
Commercial (C) and  
Industrial temperature (I)  
10  
7
mA  
mA  
V
(10)  
IIN  
Expanded (Q) temperature  
Battery voltage relative to GND, Tj = 0C to +85C  
(LX75, LX75T, LX100, LX100T, LX150, and LX150T only)  
(11)  
VBATT  
1.0  
3.6  
Commercial (C) range  
Industrial temperature (I) range  
Expanded (Q) temperature range  
0
85  
°C  
°C  
°C  
Tj  
Junction temperature operating range  
–40  
–40  
100  
125  
Notes:  
1. All voltages are relative to ground.  
2. See Interface Performances for Memory Interfaces in Table 25. The extended performance range is specified for designs not using the  
standard V  
voltage range. The standard V  
voltage range is used for:  
CCINT  
CCINT  
Designs that do not use an MCB  
LX4 devices  
Devices in the TQG144 or CPG196 packages  
Devices with the -3N speed grade  
3. Recommended maximum voltage droop for V  
is 10 mV/ms.  
must be 2.5V.  
CCAUX  
4. During configuration, if V  
is 1.8V, then V  
CCO_2  
CCAUX  
5. The -1L devices require V  
= 2.5V when using the LVDS_25, LVDS_33, BLVDS_25, LVPECL_25, RSDS_25, RSDS_33, PPDS_25,  
CCAUX  
and PPDS_33 I/O standards on inputs. LVPECL_33 is not supported in the -1L devices.  
6. Configuration data is retained even if V drops to 0V.  
CCO  
7. Includes V  
of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.  
CCO  
8. For PCI systems, the transmitter and receiver should have common supplies for V  
9. Devices with a -1L speed grade do not support Xilinx PCI IP.  
10. Do not exceed a total of 100 mA per bank.  
.
CCO  
11. V  
is required to maintain the battery backed RAM (BBR) AES key when V  
is not applied. Once V  
is applied, V  
can be  
BATT  
CCAUX  
CCAUX  
BATT  
unconnected. When BBR is not used, Xilinx recommends connecting to V  
or GND. However, V  
can be unconnected.  
CCAUX  
BATT  
DS162 (v3.0) October 17, 2011  
www.xilinx.com  
Product Specification  
3

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