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X9260TS24IZ PDF预览

X9260TS24IZ

更新时间: 2024-11-29 03:53:51
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英特矽尔 - INTERSIL 电位器
页数 文件大小 规格书
23页 338K
描述
Dual Digitally-Controlled Potentiometers

X9260TS24IZ 数据手册

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X9260  
®
Dual Supply/Low Power/256-Tap/SPI bus  
Data Sheet  
August 29, 2006  
FN8170.3  
DESCRIPTION  
Dual Digitally-Controlled (XDCP™)  
Potentiometers  
The X9260 integrates  
potentiometer (XDCP) on  
integrated circuit.  
2
digitally controlled  
monolithic CMOS  
a
FEATURES  
• Dual–Two Separate Potentiometers  
• 256 Resistor Taps/pot–0.4% Resolution  
• SPI Serial Interface for Write, Read, and Transfer  
Operations of the Potentiometer  
Wiper Resistance, 100Ω typical @ V+ = 5V,  
V- = -5V  
• 4 Nonvolatile Data Registers for Each  
Potentiometer  
• Nonvolatile Storage of Multiple Wiper Positions  
• Power-on Recall. Loads Saved Wiper Position  
on Power-up.  
The digitally controlled potentiometer is implemented  
using 255 resistive elements in a series array.  
Between each element are tap points connected to the  
wiper terminal through switches. The position of the  
wiper on the array is controlled by the user through the  
SPI bus interface. Each potentiometer has associated  
with it a volatile Wiper Counter Register (WCR) and a  
four nononvolatile Data Registers that can be directly  
written to and read by the user. The contents of the  
WCR controls the position of the wiper on the resistor  
array though the switches. Power-up recalls the  
contents of the default Data Register (DR0) to the  
WCR.  
• Standby Current <5µA Max  
• V : 2.7V to 5.5V Operation  
CC  
50kΩ, 100kΩ Versions of End to End Resistance  
• 100 yr. Data Retention  
The XDCP can be used as  
a three-terminal  
• Endurance: 100,000 Data Changes per Bit per  
Register  
• 24 Ld SOIC  
potentiometer or as a two terminal variable resistor in  
a wide variety of applications including control,  
parameter adjustments, and signal processing.  
• Low Power CMOS  
• Power Supply V  
= 2.7V to 5.5V  
CC  
V+ = 2.7V to 5.5V  
V- = -2.7V to -5.5V  
• Pb-Free Plus Anneal Available (RoHS Compliant)  
FUNCTIONAL DIAGRAM  
V
V
R
R
H1  
CC  
+
H0  
Write  
Read  
Address  
Data  
Status  
Transfer  
Inc/Dec  
Power-on Recall  
Bus  
SPI  
Bus  
Interface  
Wiper Counter  
Interface  
and Control  
Registers (WCR)  
Data Registers  
(DR0-DR3)  
Control  
V
V-  
R
R
R
R
L1  
SS  
W0  
L0  
W1  
50kΩ or 100kΩ versions  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved  
All other trademarks mentioned are the property of their respective owners  
1

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