Preliminary Information
®
X 6C64
Z8 Microcontroller Family Compatible
64K
X86C64
8192 x 8 Bit
E2 Micro-Peripheral
FEATURES
DESCRIPTION
• CONCURRENT READ WRITE™
—Dual Plane Architecture
Isolates Read/Write Functions
Between Planes
2
The X86C64 is an 8K x 8 E PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technol-
ogy. The X86C64 features a Multiplexed Address and
Data bus allowing direct interface to a variety of popular
single-chipmicrocontrollersoperatinginexpandedmul-
tiplexed mode without the need for additional interface
circuitry.
Allows Continuous Execution of Code
From One Plane While Writing in the Other
Plane
• Multiplexed Address/Data Bus
—Direct Interface to Popular 8-bit
Microcontrollers, e.g. Zilog Z8 Family
• High Performance CMOS
—Fast Access Time, 120 ns
—Low Power
The X86C64 is internally configured as two indepen-
dent 4K x 8 memory arrays. This feature provides the
ability to perform nonvolatile memory updates in one
array and continue operation out of code stored in the
other array; effectively eliminating the need for an aux-
iliary memory device for code storage.
60 mA Maximum Active
To write to the X86C64, a three byte command
sequence must precede the byte(s) being written. The
X86C64 also provides a second generation software
data protection scheme called Block Protect. Block
Protect can provide write lockout of the entire device or
selected 1K blocks. There are eight, 1K x 8 blocks that
can be write protected individually in any combination
required by the user. Block Protect, in addition to Write
Control input, allows the different segments of the
memory to have varying degrees of alterability in nor-
mal system operation.
200 µA Maximum Standby
• Software Data Protection
• Block Protect Register
—Individually Set Write Lock Out in 1K Blocks
• Toggle Bit
—Early End of Write Detection
• Page Mode Write
—Allows up to 32 Bytes to be Written in
One Write Cycle
• High Reliability
—Endurance: 10,000 Write Cycle
—Data Retention: 100 Years
FUNCTIONAL DIAGRAM
WC
CE
A12
R/W
CONTROL
LOGIC
SOFTWARE
DATA
PROTECT
DS
SEL
A12
X
L
A
T
C
H
E
S
D
E
C
O
D
E
A12
M
1K BYTES
1K BYTES
1K BYTES
1K BYTES
1K BYTES
1K BYTES
1K BYTES
1K BYTES
A8–A11
AS
U
X
Y DECODE
I/O & ADDRESS LATCHES AND BUFFERS
A/D0–A/D7
3819 FHD F02
Z8® is a registered trademark of Zilog Corporation
CONCURRENT READ WRITE™ is a trademark of Xicor, Inc.
© Xicor, 1991 Patents Pending
3819-2.1 7/29/96 T0/C1/D1 SH
Characteristics subject to change without notice
1