Preliminary Information
APPLICATION NOTE
A V A I L A B L E
AN95 • AN103 • AN107
16K/64K/128K
MPS EEPROM
X84160/640/128
Advanced MPS™ Micro Port Saver EEPROM with Block Lock™ Protection
FEATURES
bytewide memory control functions, takes a fraction of
the board space and consumes much less power.
Replacing serial memories, the µPort Saver provides all
the serial benefits, such as low cost, low power, low volt-
age, and small package size while releasing I/Os for
more important uses.
• Up to 15MHz data transfer rate
• 20ns Read Access Time
• Direct Interface to Microprocessors and
Microcontrollers
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• Low Power CMOS
—1.8V–3.6V, 2.5V–5.5V and 5V 10% Versions
—Standby Current Less than 1µA
—Active Current Less than 1mA
• Byte or Page Write Capable
The µPort Saver memory outputs data within 20ns of an
active read signal. This is less than the read access time
of most hosts and provides “no-wait-state” operation.
This prevents bottlenecks on the bus. With rates to
15MHz, the µPort Saver supplies data faster than
required by most host read cycle specifications. This
eliminates the need for software NOPs.
—32-Byte Page Write Mode
• New Programmable Block Lock™ Protection
—Software Write Protection
—Programmable Hardware Write Protection
• Block Lock (0, 1/4, 1/2, or all of the array)
• Typical Nonvolatile Write Cycle Time: 3ms
• High Reliability
—100,000 Endurance Cycles
—Guaranteed Data Retention: 100Years
• Small Package Options
—8-Lead Mini-DIP Package
—8, 14-Lead SOIC Packages
The µPort Saver memories communicate over one line of
the data bus using a sequence of standard bus read and
write operations. This “bit serial” interface allows the
µPort Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit
systems.
The X84160/640/128 provide additional data security
features through Block Lock and programmable Hard-
ware Write Protection. These allow some or all of the
array to be write protected by software command or by
hardware. System Configuration, Company ID, calibra-
tion information, or other critical data can be secured
against unexpected or inadvertent program operations,
leaving the remainder of the memory available for the
system or user access
—8, 20, 28-Lead TSSOP Packages
—8-Lead XBGA Packages
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
DESCRIPTION
The µPort Saver memories need no serial ports or spe-
cial hardware and connect to the processor memory bus.
Replacing bytewide data memory, the µPort Saver uses
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data reten-
tion is greater than 100 years.
BLOCK DIAGRAM
System Connection
Internal Block Diagram MPS
WP
H.V. GENERATION
TIMING & CONTROL
A15
µP
µC
A0
D7
DSP
ASIC
RISC
CE
I/O
OE
EEPROM
ARRAY
COMMAND
DECODE
AND
CONTROL
LOGIC
X
DEC
D0
OE
WE
16K x 8
8K x 8
2K x 8
P0/CS
P1/CLK
P2/DI
Ports
Saved
WE
P3/DO
Y DECODE
DATA REGISTER
Xicor, Inc. 1998 Patents Pending
7067 1.1 6/10/98 T10/C0/D3
Characteristics subject to change without notice
1