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X5645S14-4.5A PDF预览

X5645S14-4.5A

更新时间： 2024-01-28 21:57:27
品牌 Logo 应用领域
英特矽尔 - INTERSIL 光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
19页 312K
描述
CPU Supervisor with 64Kbit SPI EEPROM

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X5645S14-4.5A 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：PLASTIC, SOIC-14Reach Compliance Code：unknown
风险等级：5.75可调阈值：YES
模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUITJESD-30 代码：R-PDSO-G14
JESD-609代码：e0长度：8.65 mm
信道数量：1功能数量：1
端子数量：14最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE认证状态：Not Qualified
座面最大高度：1.75 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：3.9 mmBase Number Matches：1

X5645S14-4.5A 数据手册

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X5643, X5645  
®
(Replaces X25643, X25645)  
Data Sheet  
July 18, 2005  
FN8135.1  
DESCRIPTION  
CPU Supervisor with 64Kbit SPI EEPROM  
These devices combine four popular functions, Power-  
on Reset Control, Watchdog Timer, Supply Voltage  
Supervision, and Block Lock Protect Serial EEPROM  
Memory in one package. This combination lowers sys-  
tem cost, reduces board space requirements, and  
increases reliability.  
FEATURES  
• Selectable watchdog timer  
• Low V detection and reset assertion  
CC  
—Five standard reset threshold voltages  
—Re-program low V reset threshold voltage  
CC  
using special programming sequence  
Applying power to the device activates the power-on  
reset circuit which holds RESET/RESET active for a  
period of time. This allows the power supply and oscilla-  
tor to stabilize before the processor can execute code.  
—Reset signal valid to V = 1V  
CC  
• Determine watchdog or low voltage reset with a  
volatile flag bit  
• Long battery life with low power consumption  
—<50µA max standby current, watchdog on  
—<1µA max standby current, watchdog off  
—<400µA max active current during read  
• 64Kbits of EEPROM  
The Watchdog Timer provides an independent protection  
mechanism for microcontrollers. When the microcon-  
troller fails to restart a timer within a selectable time out  
interval, the device activates the RESET/RESET signal.  
The user selects the interval from three preset values.  
Once selected, the interval does not change, even after  
cycling the power.  
• Built-in inadvertent write protection  
—Power-up/power-down protection circuitry  
—Protect 0, 1/4, 1/2 or all of EEPROM array with  
™
Block Lock protection  
The device’s low V  
detection circuitry protects the  
CC  
—In circuit programmable ROM mode  
• 2MHz SPI interface modes (0,0 & 1,1)  
• Minimize EEPROM programming time  
—32-byte page write mode  
user’s system from low voltage conditions, resetting  
the system when V falls below the minimum V  
CC  
CC  
trip point. RESET/RESET is asserted until V returns  
CC  
to proper operating level and stabilizes. Five industry  
—Self-timed write cycle  
standard V  
thresholds are available, however,  
TRIP  
—5ms write cycle time (typical)  
• 2.7V to 5.5V and 4.5V to 5.5V power supply  
operation  
Intersil’s unique circuits allow the threshold to be repro-  
grammed to meet custom requirements or to fine-tune  
the threshold for applications requiring higher precision.  
• Available packages  
—8-lead PDIP, 14-lead SOIC  
BLOCK DIAGRAM  
Watchdog Transition  
Detector  
Watchdog  
Timer Reset  
WP  
Protect Logic  
RESET/RESET  
SI  
Data  
Register  
Status  
Register  
SO  
Command  
Decode &  
Control  
Reset &  
Watchdog  
Timebase  
X5643 = RESET  
X5645 = RESET  
SCK  
16Kbits  
16Kbits  
CS/WDI  
Logic  
VCC Threshold  
Reset logic  
32Kbits  
Power-on and  
Low Voltage  
Reset  
VCC  
+
-
Generation  
VTRIP  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2005. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
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