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X5648S14I-4.5A

更新时间： 2024-01-17 01:03:52
品牌 Logo 应用领域
英特矽尔 - INTERSIL 光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
18页 299K
描述
CPU Supervisor with 64Kbit SPI EEPROM

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X5648S14I-4.5A 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：PLASTIC, SOIC-14
针数：14Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.78可调阈值：YES
模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUITJESD-30 代码：R-PDSO-G14
JESD-609代码：e0长度：8.65 mm
信道数量：1功能数量：1
端子数量：14最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE认证状态：Not Qualified
座面最大高度：1.75 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：3.9 mm
Base Number Matches：1

X5648S14I-4.5A 数据手册

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X5648, X5649  
®
(Replaces X25648, X25649)  
Data Sheet  
March 17, 2005  
FN8136.0  
DESCRIPTION  
CPU Supervisor with 64Kbit SPI EEPROM  
These devices combine three popular functions, Power-  
on Reset Control, Supply Voltage Supervision, and Block  
Lock Protect Serial EEPROM Memory in one package.  
This combination lowers system cost, reduces board  
space requirements, and increases reliability.  
FEATURES  
• Low V detection and reset assertion  
CC  
—Five standard reset threshold voltages  
—Re-program low V reset threshold voltage  
CC  
using special programming sequence  
Applying power to the device activates the power-on  
reset circuit which holds RESET/RESET active for a  
period of time. This allows the power supply and oscilla-  
tor to stabilize before the processor can execute code.  
—Reset signal valid to V = 1V  
CC  
• Long battery life with low power consumption  
—<50µA max standby current, watchdog on  
—<1µA max standby current, watchdog off  
—<400µA max active current during read  
• 64Kbits of EEPROM  
The device’s low V  
detection circuitry protects the  
CC  
user’s system from low voltage conditions by holding  
RESET/RESET active when V falls below a minimum  
• Built-in inadvertent write protection  
—Power-up/power-down protection circuitry  
—Protect 0, 1/4, 1/2 or all of EEPROM array with  
CC  
V
V
trip point. RESET/RESET remains asserted until  
returns to proper operating level and stabilizes. Five  
CC  
CC  
™
Block Lock protection  
industry standard V  
thresholds are available,  
TRIP  
—In circuit programmable ROM mode  
• 2MHz SPI interface modes (0,0 & 1,1)  
• Minimize EEPROM programming time  
—32-byte page write mode  
however, Intersil’s unique circuits allow the threshold to  
be reprogrammed to meet custom requirements or to  
fine-tune the threshold in applications requiring higher  
precision.  
—Self-timed write cycle  
—5ms write cycle time (typical)  
• 2.7V to 5.5V and 4.5V to 5.5V power supply  
operation  
• Available packages  
—14-lead SOIC, 8-lead PDIP  
BLOCK DIAGRAM  
WP  
Protect Logic  
SI  
Data  
Register  
Status  
Register  
SO  
Command  
Decode &  
Control  
SCK  
CS  
16Kbits  
16Kbits  
Logic  
32Kbits  
Reset  
Timebase  
RESET/RESET  
Power-on and  
Low Voltage  
Reset  
V
+
-
CC  
X5648 = RESET  
X5649 = RESET  
Generation  
V
TRIP  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2005. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
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